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We present results of a comprehensive reliability evaluation of a 2T-2C, 4Mb, Ferroelectric Random Access Memory embedded within a standard 130nm, 5LM Cu CMOS platform. Wear-out free endurance to 5.4x10 13 cycles and data retention equivalent of 10 years at 85°C is demonstrated. The results show that the technology can be used in a wide range of applications including embedded processing.

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High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 mm 2 (130 nm node) to 0.15 mm 2 ($65 nm node). Wide signal margins, stable retention ()10 years at 85 C), and high endurance read/write cycling ()10 12 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.

We report the electrical properties of a full-bit functional 8 Mbit one transitor-one capacitor (1T-1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm 5 lm Cu interconnect complementary metal oxide semiconductor (CMOS) logic process. To increase manufacturability and reliability margins, we have introduced a single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements leading to an increased signal margin. Further, we have fabricated a digital signal processor (DSP) using the eFRAM process flow and have shown that the operating frequency is nearly the same relative to the CMOS baseline. With the development of logiccompatible eFRAM, we have created a technology platform that enables ultra-low-power devices.