Reliability Studies on Multilevel Interconnection with Intermetal Dielectric Air Gaps

Sukharev, Valeriy; Shieh, B.; Choudhury, Ratan K.; Park, Chong W.; Saraswat, Krishna C.

doi:10.1016/s0026-2714(01)00153-6

Cited by 6 publications

(3 citation statements)

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“…However, experimental results show longer electromigration lifetimes for air-gap structures. [14] In summary, air-gaps interconnects exhibit comparable or better thermal, mechanical, and electromigration reliability properties when compared to homogeneous SiO 2 based interconnects. Interested readers are referred to the available literature for further insight into this topic.…”

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 97%

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Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in airclad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed. IntroductionModern electronic systems are composed of a dense fabric of interconnect lines that connect electronic devices and chips. The scaling of transistors has resulted in miniaturization of individual devices and their interconnects. Smaller crosssectional area of electrical interconnects results in higher signal attenuation and makes data and clock recovery complex. High-speed interconnects have two primary loss mechanisms, namely metallic skin effect losses and dielectric losses. Skin effect loss is a phenomenon where, at high frequencies, the current is crowded into the near-surface region of the metal around the periphery of the conductor. As a result, the effective AC resistance per unit length of conductor increases with frequency. The second loss mechanism deals with dielectric losses. Dielectric losses are directly proportional to frequency and are therefore more pronounced at higher frequencies. Also, resistive losses in the return ground path cannot be ignored and are determined by the geometry and materials constituting the return path. Overall, dielectric losses dominate at frequencies above several GHz [1-2], as shown in Figure 1. This figure was produced with data from the International Technology Roadmap for Semiconductors (ITRS) for signal frequencies up to 50 GHz. As shown in Figure 1, the dielectric loss is more than twice that of the conductor loss at 20 GHz and the dielectric loss becomes more dominant at frequencies above 20 GHz. Thus, in order to achieve meaningful reduction in signal attenuation it is important to find ways to mitigate the dielectric loss at high frequencies. One way of achieving this goal is to use better interconnect and substrate materials.

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Section: Fabrication Of Air-gap Structuresmentioning

confidence: 97%

“…These include thermal reliability [4], electromigration reliability [14][15], dielectric reliability [16], process induced stresses [17], moisture uptake, and corrosion of metal wiring [18]. The fabrication of air-gap structure also requires a careful look at the mechanical stability of the structures.…”

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…Using low‐ k dielectric materials creates a new set of challenges for manufacturing that are currently under investigation (Mathewson et al. , 2001; Sukharev et al ., 2003).…”

Section: Low‐k Challengementioning

confidence: 99%

Circuit editing of copper and low‐k dielectrics in nanotechnology devices

Mosselveld¹,

Makarov²,

Lundquist³

et al. 2004

Journal of Microscopy

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SummaryCircuit editing of integrated circuit (IC) devices fabricated in 100-nm and smaller technologies has moved IC microsurgery into nanosurgery. Although the dimensions are challenging, an additional challenge is to mill the dielectric materials that are employed controllably. There are interesting biological similarities as carbon content and porosity increase in order to minimize the dielectric constant. These porous organic materials are extremely delicate and are readily carbonized under the ion beam. Besides minimizing carbonization, the etching of these materials must be minimized during the removal of a metallized area. A further challenge has been caused by the continuing tightening of fabrication specifications; the dielectric materials are dispersed (although not randomly) within the metallizations in order to reduce variations during a planarization process. In addition, to improve planarization tolerances, dummy metallizations are placed in regions where the need is only mechanical and not electrical. Neither of these 'extra' structures is readily available to assist in edit planning. To address these dielectrics and the structures in which they are found, several techniques -including chemistries -have been developed. Methods to increase the etching of metallization relative to the dielectric are reviewed, including chemistries that improve the selectivity of copper to dielectric.

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Airgaps in nano-interconnects: Mechanics and impact on electromigration

Zahedmanesh

Besser

Wilson

et al. 2016

Journal of Applied Physics

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In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

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Reliability Studies on Multilevel Interconnection with Intermetal Dielectric Air Gaps

Cited by 6 publications

References 0 publications

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Circuit editing of copper and low‐k dielectrics in nanotechnology devices

Airgaps in nano-interconnects: Mechanics and impact on electromigration

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