International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
DOI: 10.1109/iedm.2000.904290
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Reliability study of parasitic source and drain resistances of InP-based HEMTs

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Cited by 5 publications
(11 citation statements)
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“…The layers in the heterostructure are significantly thinner than previously studied devices that did not feature the InP etch stop [6]. In contrast with conventional InP HEMTs, these devices feature a WSiN-Ti-Pt-Au gate stack and an InP gate recess etch-stop layer in the intrinsic heterostructure [1]. The WSiN layer is 100 nm thick and is introduced to enhance the thermal reliability of the devices [11].…”
Section: Methodsmentioning
confidence: 95%
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“…The layers in the heterostructure are significantly thinner than previously studied devices that did not feature the InP etch stop [6]. In contrast with conventional InP HEMTs, these devices feature a WSiN-Ti-Pt-Au gate stack and an InP gate recess etch-stop layer in the intrinsic heterostructure [1]. The WSiN layer is 100 nm thick and is introduced to enhance the thermal reliability of the devices [11].…”
Section: Methodsmentioning
confidence: 95%
“…Most of the emphasis in this paper has been placed on the threshold voltage which is defined at a drain-to-source voltage V and a drain current mA/mm above leakage. The studied devices had gate lengths between 30 nm and 1 m [1]. The devices have been designed and optimized for the gate orientation, but there were also devices along the [011] direction.…”
Section: Methodsmentioning
confidence: 99%
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