2011
DOI: 10.1016/j.tsf.2010.12.094
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Reliable and low-voltage electrowetting on thin parylene films

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Cited by 55 publications
(45 citation statements)
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“…Parylene C (chlorinated) and Parylene HT (fluorinated) were the two options used for the dielectric. Parylene C was vapor deposited with a Specialty Coating Systems 2010 lab coater, whereas for Parylene HT ITO-coated glass slides were sent to Specialty Coating Systems (Indianapolis, USA) for coating [29]. Cytonix Fluoropel 1601V and Asahi Cytop 809M (1wt% solution in fluorosolvent Ct. Solv.…”
Section: Methodsmentioning
confidence: 99%
“…Parylene C (chlorinated) and Parylene HT (fluorinated) were the two options used for the dielectric. Parylene C was vapor deposited with a Specialty Coating Systems 2010 lab coater, whereas for Parylene HT ITO-coated glass slides were sent to Specialty Coating Systems (Indianapolis, USA) for coating [29]. Cytonix Fluoropel 1601V and Asahi Cytop 809M (1wt% solution in fluorosolvent Ct. Solv.…”
Section: Methodsmentioning
confidence: 99%
“…The arrangement represents two capacitors in series with the water droplet as one electrode of each capacitor. Both capacitors consist of the water droplet, a 3.5 m thick Parylene C layer each (from SCS coatings, Indianapolis, Indiana, USA) [47][48][49] as the dielectric layer, and two structured ITO contact layers each, such that there are two front (1a, 1b in Figure 2) and two rear ITO structures (2a, 2b in Figure 2). The sub-and the superstrate were purchased from Sigma Aldrich, St. Louis, Missouri, USA, as 1.1 mm thick glass slides covered with a 20 nm thick ITO film.…”
Section: Device Layout Materials and Technologymentioning
confidence: 99%
“…Wires that connect to electrodes on the 3-phase buses must span the entire array, essentially blocking the ability of other wires to escape from the perimeter on the same PCB layer. To eliminate this problem for the pin-optimized version, we removed the two side buses and use separate three-phase buses (Pins 1-3, [4][5][6][7][8][9] to control the three remaining buses, as shown in Fig. 7(a).…”
Section: B Co-optimizing Pin Assignment and Wire Routingmentioning
confidence: 99%
“…We do not consider the cost of circuitry to amplify the voltage produced by the microcontroller to levels appropriate to drive the DMFB. Typical actuation voltages are in the 50-70 V range [28], [30]; low voltage devices that operate at ∼15 V have also been reported [9], [26] …”
Section: A Wire Routing Cost Analysismentioning
confidence: 99%