Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators

Logic BIST is a safety mechanism, which performs testing for Automotive electronics. However, pseudorandom LBIST patterns results in increased test time and test power. In this letter, a novel time multiplexed LBIST is presented to overcome test related problems of AI accelerators. First, the accelerator array is divided into smaller sub arrays, which are tested on time multiplexed clock cycles. This: 1) improves overall test time, under the given test power limit, 2) allows reduction in shift power, under given test time limits and 3) since only one sub array is clocked at a time, the peak power is reduced.

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Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators

Cited by 2 publications

References 23 publications

Master-slave based test cost reduction method for DNN accelerators

Master-slave based test cost reduction method for DNN accelerators

Time multiplexed LBIST for in-field testing of automotive AI accelerators

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