Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects

Shah, H. Naitoandarvindv .; Shiu, Pun Hang; Bell, B.; Aldredge, Mamie; Sopory, Namarata; Davis, J.A.

doi:10.1145/774572.774614

Cited by 20 publications

(2 citation statements)

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“…The international technology roadmap for semiconductor report on interconnect indicated that crosstalk noise will become the dominant problem affecting propagation delays, hence degrading overall system performance [1]. Techniques to avoid the crosstalk delay have been proposed by many researchers [2–9]. These methods are applied on different levels of the design; physical level solutions include wire sizing optimisation, shield insertion and repeater insertion [6, 10].…”

Section: Introductionmentioning

confidence: 99%

“…Techniques to avoid the crosstalk delay have been proposed by many researchers [2–9]. These methods are applied on different levels of the design; physical level solutions include wire sizing optimisation, shield insertion and repeater insertion [6, 10]. Other techniques are implemented on the data link layer; this consists of data encoding to avoid crosstalk [7].…”

Section: Introductionmentioning

confidence: 99%

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Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation

Halak

2014

IET Computers & Digital Techniques

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Abstract. Modern interconnect performance is greatly affected by crosstalk noise due continuous decrease in wire separation and increase in its aspect ratio with technology scaling. Such noise is highly dependent on data transition patterns, coding techniques have been proposed to alleviate crosstalk delay by controlling these patterns. The complexity of available crosstalk avoidance codes, along with their associated overheads, increase rapidly with bus width. The lack of energy and area efficient method to implement such cods has so far prevented their use in practical designs. This paper presents a generic framework which allows efficient implementations of crosstalk avoidance codes; the essence of the proposed approach is based on the partial coding concept. Quantitative analysis performed in 32nm technology shows that substantial savings in area and energy costs can be obtained using the proposed technique compared with both existing coding solutions and conventional methods as shielding and repeater insertion.

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Section: Introductionmentioning

confidence: 99%