Repeater insertion to minimise delay in coupled interconnects

Abstract

Signalling over long interconnect is a dominant issue in electronic chip design in current technologies, with the device sizes getting smaller and smaller and the circuits becoming ever larger. Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced closer and closer together and signal rise and fall times go into the sub-nano second region, the coupling between interconnects assumes great significance. The resulting cross talk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. In this paper we attempt to quantify the effect of worst-case capacitive cross talk in parallel buses and look at how it affects repeater insertion in particular. We develop analytic expressions for the delay, buffer size and number that are suitable in a-priori timing analyses and signal integrity estimations. All equations are checked against a dynamic circuit simulator (SPECTRE).

Thermal analysis of on-chip interconnects in multicore systems

“…This increase in delay is compensated by inserting repeaters at optimal locations [9] and splitting the long-range link into different segments. Each such segment is connected to the silicon through vias at either ends.…”

A Data Capturing Method for Buses on Chip

“…Among others, existing work suggests driver scaling, wire width and spacing optimization [1], [2], [13], [15], [60]. Popular techniques are based on repeater insertion [3], [14], [32]- [34], [42]. Although effective, power consumption along with tedious silicon area allocation and placement of buffers on a line complicate the latter approach.…”

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

“…More concerns arise for especially long interconnects [5]. Repeaters, which divide a long interconnect into shorter sections, have been proposed and have successfully resolved the problems by improving the interconnect delay [6,7,8,9,10]. However, repeaters generate other problems: finding the optimal number and size of the repeaters has been nontrivial and additional power and area is required.…”

“…Particularly, following the input signal on its critical path, a boosting signal that is identical to the original input signal is routed to the inner gate of the IGAA device to lower V th in advance. When distributing the digital signals inside the chip, the most popular design approach for reducing propagation delay is to introduce intermediate repeaters in the interconnect line [6,7,8,9,10]. To decrease the interconnect delay in modern IC design, a long interconnect is divided evenly into smaller segments with repeaters inserted between each segment (each repeater is responsible for driving one segment).…”