Requirements, bottlenecks, and good fortune: agents for microprocessor evolution

Patt, Yale N.

doi:10.1109/5.964437

Cited by 19 publications

(6 citation statements)

References 4 publications

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“…Figure 7 overviews the evolution of the SRAM cell from a transistor structural perspective. In 1971, Intel introduced the 4004 microprocessors based on 12 µm channel length transistors [ 75 ]. Later, in the early 1980s, polycide-gate and silicide resolved issues of the increasing gate and source/drain resistance [ 76 ].…”

Section: Finfet 6t-sram Cellmentioning

confidence: 99%

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

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Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

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Section: Finfet 6t-sram Cellmentioning

confidence: 99%

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

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“…When we say "microprocessor today" we generally assume the shaded region of Fig. 17.a, where each microprocessor consists of circuit that implement hardware structure (collectively called the microarchitecture) that provide an interface (called ISA) to the software [25]. As it can be seen from Fig.…”

Section: Microprocessor Today -Microprocessor Tomorrowmentioning

confidence: 99%

“…If we take our levels of transformation and include the algorithm and language into microprocessor, the microprocessor then becomes the thing that uses device technology to solve the problem (see Fig. 17.b) [25].…”

Section: Microprocessor Today -Microprocessor Tomorrowmentioning

confidence: 99%

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

2004

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In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, microarchitecture, architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as "Moore Law". Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the microarchitectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution, out-of-order execution, etc.), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc.). In addition, the paper also discusses microarchitectural techniques likely to be used in the near future such as microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques intended for minimization of power consumption.

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“…Effective instruction delivery is vital for superscalar processors operating at high clock frequencies [Patt 2001;Ronen et al 2001]. The rate and accuracy at which instructions enter the processor pipeline set an upper limit to sustained performance.…”

Section: Introductionmentioning

confidence: 99%

Block-aware instruction set architecture

Zmily

Kozyrakis

2006

ACM Trans. Archit. Code Optim.

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Instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle instruction-cache accesses, and target or direction mispredictions for control-flow operations. This paper presents a block-aware instruction set (BLISS) that allows software to assist with front-end challenges. BLISS defines basic block descriptors that are stored separately from the actual instructions in a program. We show that BLISS allows for a decoupled front-end that tolerates instruction-cache latency, facilitates instruction prefetching, and leads to higher prediction accuracy.

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Requirements, bottlenecks, and good fortune: agents for microprocessor evolution

Abstract: The first microprocessor, the Intel 4004, showed up in 1971

Cited by 19 publications

References 4 publications

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Block-aware instruction set architecture

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