Research of Bulk Erase Operation in Vertical Three-Dimensional Cell Array Architecture

Abstract

A bit-cost scalable (BiCS) NAND flash memory with a bulk erasing method is investigated in view of cell characteristics and uniformity. The proposed cell array has an additional electrode layer for a bulk erase operation in the middle of a vertical channel string cell. Here, under a bias condition of 20 V, a programming threshold voltage of 4.2 V at 1 ms and an erasing threshold voltage of V th = -1.5 V at 10 ms are confirmed, which is acceptable for flash memories. Furthermore, the shielding transistor close to an erase electrode is also investigated, which gives better erase characteristics for the cells adjacent to the erase electrode. From this result, we expect that a bulk erasable-BiCS technology with a shielding transistor can be a candidate three-dimensional (3D) NAND flash memory.

Device characteristics of the select transistor in a vertical-NAND flash memory

“…[4][5][6][7][8][9] However, the scaling limitation and manufacturing difficulties will be confronted in the near future for conventional NAND technology. In order to overcome these problems, several three-dimensional (3D) technologies, such as Bit-Cost Scalable (BiCS), [10][11][12][13][14][15][16][17][18] SMArT 19,20) and terabit cell array transistor (TCAT) flash technologies, 13,21,22) have been introduced. The TCAT structure has advantages over the BiCS structure, especially with respect to the gate structure and word line resistance.…”