Resistance and electromigration performance of 6 nm wires

Chawla, J. S.; Sung, Soo Hak; Bojarski, Stephanie A.; Carver, Colin T.; Chandhok, Manish; Chebiam, Ramanan; Clarke, James Stanier; Harmes, M.; Jezewski, Chris J.; Kobrinski, M. J.; Krist, B.; Mayeh, Mona; Turkot, R. B.; Yoo, Hye Jin

doi:10.1109/iitc-amc.2016.7507682

Cited by 23 publications

(9 citation statements)

References 5 publications

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“…The mean values for the parameters are obtained from recent experimental reports on modern manufacturing processes [4][5][6][7]. This model confirms that for novel technologies [12][13][14][15][16][17], neglecting the temperature evolution and its impact on interconnect reliability and their lifetime may lead to wrong conclusions or catastrophic failures.…”

Section: Materials Migrationsupporting

confidence: 68%

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Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Abbasinasab

Marek-Sadowska

2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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We investigate the effect of electrically induced thermal load on interconnect reliability and aging. We propose new models for uniform and non-uniform temperature evolution and its steady state distribution in interconnects considering Joule heating and heat convection. The models are verified by comparing the results against those of finite element experiments. We apply our models to study material migration induced aging and failures. We discuss how different non-uniform temperature profiles affect interconnect lifetime. We propose new formulas for accurate temperature aware assessment of the mortality of interconnects. We demonstrate that neglecting thermal effects in modern technologies may lead to incorrect conclusions about interconnect mortality. We also provide a method for modeling the true mean time to failure based on underlying physics.

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Section: Materials Migrationsupporting

confidence: 68%

“…Branches carry current densities of the order of 1MA/cm 2 . The segment is then properly constructed in COMSOL Multiphysics [12]. The values for geometrical, electrical, mechanical and thermal properties of technology are obtained from various recent reports of major foundries for 10nm [4][5][6] [13][14][15][16][17].…”

Section: Temperature In Interconnectsmentioning

confidence: 99%

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Abbasinasab

Marek-Sadowska

2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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“…1,2 This well-known resistivity size effect is due to increased electron scattering at the conductor surfaces [3][4][5][6] and grain boundaries, [7][8][9][10][11] and is exacerbated by surface roughness. [12][13][14] The resistivity increase has become a major challenge for the continued downscaling of Cu interconnects in integrated circuits, 15,16 and as a result, considerable ongoing research efforts focus on improving the Cu line conductivity 5,6,8,17,18 and on evaluating possible replacement materials. 15,[19][20][21][22][23][24][25] Particularly promising are metals that have a small resistivity size effect and therefore may have a lower resistivity than Cu in the case of narrow wires.…”

Section: Introductionmentioning

confidence: 99%

Resistivity size effect in epitaxial Ru(0001) layers

Milosevic

Kerdsongpanya

Zangiabadi

et al. 2018

Journal of Applied Physics

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Epitaxial Ru(0001) layers are sputter deposited onto Al2O3(0001) substrates and their resistivity ρ measured both in situ and ex situ as a function of thickness d = 5-80 nm in order to quantify the resistivity scaling associated with electron-surface scattering. All layers have smooth surfaces with a root-mean-square roughness < 0.4 nm and exhibit an epitaxial relationship with the substrate: Ru[0001]║Al2O3[0001] and Ru[ 0 1 10 ]║Al2O3[ 0 2 11 ], suggesting negligible resistivity contributions from geometric surface roughness and grain boundary scattering. The room temperature ρ vs d data is well described by the semiclassical Fuchs and Sondheimer (FS) model, indicating a bulk electron mean free path λ = 6.7 ± 0.3 nm. Electron scattering at the Ru(0001) surface is distinctly different from the known Cu(001) surface: Its scattering specularity is unaffected by oxygen exposure but dependent on temperature and/or the environment, as indicated by a 43% decrease in the measured ρo×λ product with decreasing temperature from 295 to 77 K. Transport simulations employing the ruthenium electronic structure determined from firstprinciples and a constant relaxation time approximation indicate that the resistivity is strongly (by a factor of two) affected by both the transport direction and the terminating surfaces. This is quantified with a room temperature effective mean free path λ * which is relatively small for transport along the hexagonal axis independent of layer orientation (λ * = 4.3 nm) and for (0001) terminating surfaces independent of transport direction (λ * = 4.5 nm), but increases, for example, to λ * = 8.8 nm for (1120) surfaces and transport along [1100]. Direct experiment-simulation comparisons show a 12% and 49% higher λ from experiment at 77 and 295 K, respectively, indicating limitations of the semi-classical transport simulations despite the correct accounting of Fermi surface and Fermi velocity anisotropies. The overall results demonstrate a low resistivity scaling for Ru, suggesting that 10 nm half-pitch Ru interconnect lines are approximately 2 times more conductive than comparable Cu lines.

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“…Furthermore, this method promotes lower via-resistance through barrier thickness reduction, which proves it to be a viable Cu-barrier candidate for the 5-nm node and beyond. However, this approach would only be a short-term alternative due to a size effect of Cu resistivity and TaN high resistance [146].…”

Section: Beol For Nano-scale Transistorsmentioning

confidence: 99%

“…The direct contact of Co and Cu at the bottom without TaN/Ta barrier interface results in a reduction of via-resistance. Moreover, Co is expected to have a better EM performance compared to Cu due to its higher melting point [143,146,149,150].…”

Section: Beol For Nano-scale Transistorsmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Resistance and electromigration performance of 6 nm wires

Cited by 23 publications

References 5 publications

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Resistivity size effect in epitaxial Ru(0001) layers

Miniaturization of CMOS

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