Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Parihar, Narendra; Sharma, Uma; Mukhopadhyay, Subhadeep; Goel, Nilesh; Chaudhary, Ankush; Rao, Rakesh; Mahapatra, S.

doi:10.1109/irps.2017.7936415

Cited by 27 publications

(8 citation statements)

References 31 publications

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“…We observe saturating Δ V th for long t str even for high V GSTR / T (−2.5 V/75 °C) stress conditions, unlike the back-gated devices, as shown in the earlier section. Degradation due to hole trapping has lower E A compared with degradation due to trap generation . This is verified from Figure b where Δ V th,max is plotted as a function of T on a semilog scale, indicating its Arrhenius dependence on T .…”

Section: Resultssupporting

confidence: 55%

Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Goyal

Parihar

Jawa

et al. 2019

ACS Appl. Mater. Interfaces

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Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al2O3, SiO2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage (V th) instability under negative gate bias stress at various measurement delays (t m), stress biases (V GSTR), temperatures (T), and stress times (t str) for the first time. Thin top-gated oxide enables low V GSTR that is closer to the operating condition and ultrafast V th measurements with low delay (t m = 10 μs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of V th degradation (ΔV th) shows fast saturation at longer stress times and low-temperature activation energy. V th instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different V GSTR and T. It is shown that measurements using larger t m show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying t m (1 ms being the lowest due to a low drain current level for thick oxide), V GSTR, and T to benchmark our top-gated results. Nonsaturating ΔV th in the back-gated devices is shown to result from recovery artifacts due to the large t m (1 ms and greater) values. Finally, using a V GSTR and T-dependent first-order model, we show that the top-gated Al2O3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.

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Section: Resultssupporting

confidence: 55%

Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Goyal

Parihar

Jawa

et al. 2019

ACS Appl. Mater. Interfaces

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“…This result also helps confirm that the rapid recoverable components have lower E A than V IT and V OT . Hence, the fractional V HT with the time constants smaller than 1 µs contribution would go up at the lower temperature, resulting in lower n [29], [33]. On the other hand, V th at the recovery phase with t r = 1 µs are also plotted in Fig.…”

Section: B Characterization Of Nbti Behaviors In Si Pfinfets By Fvm mentioning

confidence: 96%

“…Such a phenomenon is inconsistence with the comprehensive R-D framework. On the other hand, the slight increase of n at larger |V str | indicates the contribution of V OT , which is also significant at harsher stress conditions [29], [33]. Hence, the decrease of the rapid recoverable components at longer time could be attributable to the neutralization of defects by capturing the electron emitted from the deep traps in high-k layer.…”

Section: B Characterization Of Nbti Behaviors In Si Pfinfets By Fvm mentioning

confidence: 98%

“…According to previous studies on NBTI models, the rapid recoverable components should be attributable to the V HT with the time constants smaller than 1 µs and lower activation energy E A . Furthermore, in the R-D framework, the subcomponent of V HT should become saturated after longer time, and the subcomponents ( V HT , V IT , and V OT as the contribution of new gate insulator traps generations) are assumed to be uncorrelated [29], [33]. However, it is observed in Fig.…”

Section: B Characterization Of Nbti Behaviors In Si Pfinfets By Fvm mentioning

confidence: 99%

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Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs

Liu

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, NBTI behaviors of Si pFinFETs are characterized with the measurement time down to ns-scale utilizing the fast V th measurement (FVM) technique. It is found that the NBTI behaviors in terms of V th shift is strongly influenced by the measurement speed even in the nano-second scale (ns-scale). The measurement phase itself during the NBTI characterization could bring in an additional V th shift (V th) or V th recovery. From the ns-scale characterization results in different stress and temperature, it is shown that the rapid recoverable components of NBTI should be attributable to the rapid hole trapping/detrapping, which are related to the defects with time constants of ns-scale. INDEX TERMS pFinFETs, reliability, NBTI, ultra-fast measurement.

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“…Charge trapping at the gate dielectric layer along with the dangling bonds generation at the oxide/channel interface are known to be the main origins of electronic device reliability issues such as bias temperature instability (BTI) [1][2][3][4][5][6][7][8][9][10]. Such charge trapping and transport process is also important to oxide protection layer in electrochemical cells.…”

Section: Introductionmentioning

confidence: 99%

Ab Initio Investigation of Charge Trapping Across the Crystalline- Si –Amorphous- SiO2 Interface

et al. 2019

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Accurate microscopic description of the charge trapping process from semiconductor to defects in dielectric oxide layer is of paramount importance to understanding many microelectronic devices like the complementary metal-oxide-semiconductor (CMOS) transistors, as well as electrochemical reactions. Unfortunately, most current microscopic descriptions of such processes are based on empirical models with parameters fitted to experimental device performance results or simplified approximations like the Wentzel-Kramers-Brillouin (WKB) method. Some critical questions are still unanswered, including: What controls the charge hopping rate, the coupling strength between the defect level to semiconductor level, or the energy difference? How does the hopping rate decay with defect-semiconductor distance? What is the fluctuation of the defect level, especially in amorphous dielectrics? Many of these questions can be answered by ab initio calculations. However, till date, there are scarce ab initio studies for this problem mainly due to technical challenges from atomic structure construction to large system calculations. Here, using the latest advance in calculation methods and codes, we have studied the carrier trapping problem using density functional theory (DFT) based on the Heyd-Scuseria-Ernzerhof (HSE) exchange correlation functional. The valence bond random switching method is used to construct the crystalline-Si/amorphous-SiO 2 (c-Si/a-SiO 2) interfacial atomic structure, the HSE yields band offset agrees well with experiments. The hopping rate is calculated with the Marcus theory, and the hopping rate dependences on the gate potential and defect distances are revealed, as well as the range of fluctuation results from amorphous structural variation. We have also analyzed the result with the simple WKB model and found major difference in the description of the coupling constant decay with the defect-semiconductor distance. Our results provide the ab initio simulation insights for this important carrier trapping process for device operation.

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Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Cited by 27 publications

References 31 publications

Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs

Ab Initio Investigation of Charge Trapping Across the Crystalline- Si –Amorphous- SiO2 Interface

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Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Cited by 27 publications

References 31 publications

Accurate Threshold Voltage Reliability Evaluation of Thin Al2O3 Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Accurate Threshold Voltage Reliability Evaluation of Thin Al2O3 Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs

Ab Initio Investigation of Charge Trapping Across the Crystalline- Si –Amorphous- SiO2 Interface

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Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses

Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses