Reversible logic implementation of AES algorithm

Datta, Kamalika; Shrivastav, Vivek Kumar; Sengupta, Indranil; Rahaman, Hafizur

doi:10.1109/dtis.2013.6527794

Cited by 18 publications

(2 citation statements)

References 15 publications

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“…Reversible sequential circuits and memories have also been proposed [18–21]. Few applications have been investigated from the domains of image processing [22, 23], cyptography [24–26] and FEC [27]. Synthesis methodologies for reversible circuits have been proposed in [28–30].…”

Section: Basics Of Reversible Logicmentioning

confidence: 99%

LDPC check node implementation using reversible logic

Awais

Razzaq

Ahmed

et al. 2019

IET Circuits, Devices & Systems

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Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal-oxide-semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm 2 , achieves up to 4.3 GHz frequency and consumes 52 μW power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

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Section: Basics Of Reversible Logicmentioning

confidence: 99%

LDPC check node implementation using reversible logic

Awais

Razzaq

Ahmed

et al. 2019

IET Circuits, Devices & Systems

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“…The basic thought of a cipher structure is constructed with reversible gates is proposed in [7]. Fig 7 will display the Basic scheme of cipher for Encryption/Decryption of a data.…”

Section: Operation Of the Encryption With Rrgmentioning

confidence: 99%

FPGA Implementation of Encryption and Decryption of a Message using Optimized Reconfigurable Reversible Gate

Rajesh¹,

Reddy²

2019

IJRTE

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The prime incentive to learn reversible computation is that it is the best efficient way to reduce heat dissipation than any other conventional methods. The major condition for reversibility is that there is a one-to-one connection between each input and output vectors and it has received a huge significance because of there no information loss throughout the reversible computation which results in reduces the power dissipation. Here, we proposed the design of encryption/decryption of the data schemes by using reversible computing. In this regard, a basic building block is designed for encryption design is simply cascading of a 4-bit reversible gates and it is performed every 4-variable reversible functions, for this intention a new reconfigurable reversible gate (RRG) is proposed and is designed with the use of basic reversible gates like NOT gate, CNOT gate, Toffoli gate, and Fredkin gates. In this work, the encryption/decryption of an 8-bit data is proposed and the Simulation results of encryption/decryption of the circuits using reversible gates are also presented. The gate count, delay, constant inputs, and the garbage outputs are calculated. The complete Simulation and the synthesis process can be finished with the Xilinx ISE 14.7 version and it is dumped on the FPGA Zynq board.

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