RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Jan, C.-H.; Agostinelli, M.; Deshpande, H.; El‐Tanani, Mohamed; Hafez, W.; Jalan, U.; Janbay, L.; Kang, Min-Ho; Lakdawala, Hasnain; Jiang, Lin; Lu, Yung-Hsiang; Mudanai, S.; Park, J.; Rahman, Anisur; Rizk, J.; Shin, Woorim; Soumyanath, K.; Tashiro, Hiroyuki; Tsai, C.; Vandervoorn, P.; Yeh, J.-Y.; Bai, P.

doi:10.1109/iedm.2010.5703431

Cited by 77 publications

(32 citation statements)

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“…As predicted by simulation in Section III, the 50Ω noise figure is 1-2 dB larger than that measured in a 45nm PD-SOI TIA with unitary gain 50Ω output driver [11] suggesting that noise figure no longer improves with scaling from 45nm to 28nm SOI CMOS. This trend has been observed in other bulk and FinFET CMOS technologies [21], [22].…”

Section: Resultsmentioning

confidence: 61%

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Shopov

2016

IEEE J. Solid-State Circuits

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A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 VPP with a measured input sensitivity of 10 mVPP at 40 Gb/s, and requires at least 40mVPP input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the >4V PP swing seriesstacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-toRx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.

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Section: Resultsmentioning

confidence: 61%

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Shopov

2016

IEEE J. Solid-State Circuits

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“…23(a). This is attributed to the continued scaling of gate oxide [51]. This figure also shows that thick gate devices have higher normalized input referred voltage noise than thin gate devices for all the technology nodes due to the reduced C ox caused by the use of thicker oxide.…”

Section: Phase Noise Analysismentioning

confidence: 75%

Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs

Elabd

Khalil

2016

Integration

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“…6[tm,Nr=50). The values of NFmin are higher than for our technology geometry, and the following reasons may be given: (i) NFmin was uncorrected for thermal noise and pad parasitic contributions [3], (ii) NFmin is negatively impacted by the huge number of gate fingers (Nr=300) which contributes to greatly decrease fmaxo through an increase of parasitic fringe capacitances [12] (see also Fig.3 in [13], the variations of fmax as a function of W tot, for different W u and N f as parameter). NFmin is also reported in Fig.6.B for the same technology as the one described in [3], but corresponding to a previous node (45-nm) [12] (and probably a RF transistor better optimized); in this case, our extracted NFmin data are in line with those reported.…”

Section: A Rf Ssec Extractionmentioning

confidence: 97%

RF noise investigation in High-k/Metal Gate 28-nm CMOS transistors

Tagro

Poulain

Lepilliet

et al. 2012

2012 IEEE/MTT-S International Microwave Symposium Digest

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In order to pursue Moore's law, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate (H-kIMG) for CMOS has been a key point to downscale the "equivalent oxide thickness" (EOT). Within this context, this paper intends to investigate RF noise performance of a recent Low Power (LP) 28-nm H-kIMG CMOS Technology. For this purpose, S-parameters have been measured up to 110GHz to accurately extract an RF Small Signal Equivalent Circuit (SSEC), required to extract a two-temperature noise model. The technology offers a minimum noise figure NFmin of O.8dB (with an associated gain G. equal to 14dB) @20GHz, for a DC drain current of 13SmA/mm: these performances well compete with those previously reported for other H-kIMG technology.

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RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Cited by 77 publications

References 0 publications

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs

RF noise investigation in High-k/Metal Gate 28-nm CMOS transistors

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