RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation

Magoon, R.; Molnar, Alyosha

doi:10.1109/rfic.2002.1011502

Cited by 29 publications

(16 citation statements)

References 5 publications

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“…The DIV2 circuit is realized using conventional differential CMLtype D flip-flops. As compared to single-ended DIV3 circuits implemented in BJTs [5], the differential CMOS DIV3 architecture shown in Fig. 1 (c) generates a 50% duty cycle clock with much less power and area but with higher signal integrity.…”

Section: Circuit Designmentioning

confidence: 99%

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

Kim

2010

IEICE Electron. Express

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Abstract:A low-power wideband frequency synthesizer that generates multiple LO frequencies for mobile TV tuner ICs is presented. The synthesizer utilizes a single on-chip LC VCO and an odd-order frequency division technique to achieve both low power and small silicon area. The integrated LC VCO has a tuning range of 2.3 to 3.85 GHz. With a division ratio of 2, 4, 6, 12, 16, 24, and 32, the LO generation block supports FM, VHF III, UHF, Europe-L, and USA-L bands. The measured LO phase noise for the L-band is under −79 dBc/Hz at an offset of 10 kHz. The synthesizer implemented in 0.18-µm CMOS technology occupies an area of about 1.2 mm 2 and dissipates up to 33.5 mW from a 1.8-V supply.

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Section: Circuit Designmentioning

confidence: 99%

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

Kim

2010

IEICE Electron. Express

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“…Another option might have been cancellation of harmonics as proposed in [11] for example, but this would lead to increased complexity and power consumption.…”

Section: B Divide-by-5 With Quadrature Outputsmentioning

confidence: 99%

A Fast-Hopping Single-PLL 3-Band MB-OFDM UWB Synthesizer

Beek

Leenaerts

Weide

2006

IEEE J. Solid-State Circuits

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“…The proposed currentswitchable emitter couple-logic D flip-flop, shown in Fig. 1, has been utilized in a divide-by-three prescaler with a 50% duty cycle [8][9]. This current-switchable D flip-flop can form any 50% duty-cycle divide-by-N prescaler, according to our design concept.…”

Section: Introductionmentioning

confidence: 99%

True 50% duty-cycle high-speed divider with the modulus of odd numbers

Tseng

Wei

Syu

et al. 2009

2009 Asia Pacific Microwave Conference

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This paper proposes a true 50% duty-cycle highspeed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 µm SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.Index Terms -50% duty cycle, divide-by-N, prescaler, SiGe HBT.

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RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation

Cited by 29 publications

References 5 publications

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

A Fast-Hopping Single-PLL 3-Band MB-OFDM UWB Synthesizer

True 50% duty-cycle high-speed divider with the modulus of odd numbers

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