Rfuzz

Laeufer, Kevin; Koenig, John; Kim, Dong-Gyu; Bachrach, Jonathan; Sen, Koushik

doi:10.1145/3240765.3240842

Cited by 88 publications

(8 citation statements)

References 12 publications

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“…While constraint-based approaches can be effective, they require significant effort in order to set up high-quality testbenches. Inspired from the ongoing success story of modern coverage-guided fuzzing techniques in the SW domain, fuzzing has been adopted to enable test generation for HW designs at the RTL [16]. Motivated by the promising results further research has been sparked that optimized the fuzzing approach by employing directed test generation for guidance [17] and taking RTL specific characteristics into account [18].…”

Section: Related Workmentioning

confidence: 99%

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Ahmadi-Pour,

Logemann,

Herdt

et al. 2023

Chips

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In this paper, we propose a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. In particular, we combine two approaches that complement each other and use the VP as a readily available reference model: We use (A) Coverage-Guided Fuzzing (CGF) which enables comprehensive verification at the unit-level of the Register-Transfer Level (RTL) HW peripheral with a Transaction Level Modeling (TLM) reference, and (B) an application-driven co-simulation-based approach that enables verification of the HW peripheral at the system-level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract TLM PLIC implementation from the open source RISC-V VP as the reference model. In our experiments we find three behavioral mismatches and discuss the observation of these, as well as non-functional timing behavior mismatches, that were found through the proposed synergistic approach. Furthermore, we provide a discussion and considerations on the RTL/TLM Transactors, as they embody one keystone in cross-level methods. As the different approaches uncover different mismatches in our case-study (e.g., behavioral mismatches and timing mismatches), we conclude a synergy between the methods to aid in verification efforts.

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Section: Related Workmentioning

confidence: 99%

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Ahmadi-Pour,

Logemann,

Herdt

et al. 2023

Chips

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“…In fact, due to masking effects and the inevitable information loss introduced by many classical gates, the chance of detecting differences in the circuits within a few arbitrary simulations is greatly reduced (e.g., x ∧ 0 masks any difference that potentially occurs during the calculation of x). Consequently, sophisticated schemes for constraint-based stimuli generation [47]- [50], fuzzing [51], [52], etc. are employed in order to verify classical circuits.…”

Section: The Power Of Simulationmentioning

confidence: 99%

Decision Diagrams for Quantum Computing

Wille

Hillmich

Burgholzer

2022

Design Automation of Quantum Computers

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Quantum computing promises to solve some important problems faster than conventional computations ever could. Currently available NISQ devices on which first practical applications are already executed demonstrate the potential-with future fault-tolerant quantum hardware for more demanding applications on the horizon. Nonetheless, the advantages in computing power come with challenges to be addressed in the design automation and software development community. In particular, non-quantum representations of states and operations, which provide the basis, e.g., for quantum circuit simulation or verification, require an exponential amount of memory. We propose to use decision diagrams as data structure to conquer the exponential memory requirements in many cases. In this chapter, we review the fundamentals on decision diagrams and highlight their applicability in the tasks of quantum circuit simulation with and without errors as well as in verification of quantum circuits. The tools presented here are all available online as open source projects.

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“…Finally, validity feedback has been useful in fuzzing digital circuits that have constrained interfaces [48], as well as in generating seed inputs for conventional fuzzing [70].…”

Section: Related Workmentioning

confidence: 99%

Semantic fuzzing with zest

Padhye

Lemieux

Sen

et al. 2019

Proceedings of the 28th ACM SIGSOFT International Symposium on Software Testing and Analysis

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107

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Programs expecting structured inputs often consist of both a syntactic analysis stage, which parses raw input, and a semantic analysis stage, which conducts checks on the parsed input and executes the core logic of the program. Generator-based testing tools in the lineage of QuickCheck are a promising way to generate random syntactically valid test inputs for these programs. We present Zest, a technique which automatically guides QuickCheck-like randominput generators to better explore the semantic analysis stage of test programs. Zest converts random-input generators into deterministic parametric generators. We present the key insight that mutations in the untyped parameter domain map to structural mutations in the input domain. Zest leverages program feedback in the form of code coverage and input validity to perform feedback-directed parameter search. We evaluate Zest against AFL and QuickCheck on five Java programs: Maven, Ant, BCEL, Closure, and Rhino. Zest covers 1.03×-2.81× as many branches within the benchmarks' semantic analysis stages as baseline techniques. Further, we find 10 new bugs in the semantic analysis stages of these benchmarks. Zest is the most effective technique in finding these bugs reliably and quickly, requiring at most 10 minutes on average to find each bug. CCS CONCEPTS• Software and its engineering → Software testing and debugging. KEYWORDSStructure-aware fuzzing, property-based testing, random testing ACM Reference Format:

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Rfuzz

Cited by 88 publications

References 12 publications

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Decision Diagrams for Quantum Computing

Semantic fuzzing with zest

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