RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router

Li, Cunlu; Dong, Dezun; Lu, Zhonghai; Liao, Xiangke

doi:10.1109/tpds.2018.2817552

Cited by 19 publications

(8 citation statements)

References 19 publications

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“…The evaluated results illustrate that our design can accomplish 46% and 15.7% performance enhancement in packet latency under synthetic traffic and traces from PARSEC than TS-Router, and the cost of energy and area is reasonable. Furthermore, average packet latency is decreased by our two successful approaches and uniform traffic is 13% and 17% respectively [13].…”

Section: Literature Surveymentioning

confidence: 78%

NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

S.B¹

2020

IJATCSE

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To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia data at low latency and high throughput. These NoC's was designed and developed the chips for both 2D and 3D which includes switching, routing and crossbar techniques, out of which routing algorithms are plays major role due to the computational operations take place here and produce the different delay. In turn these delays are affected on throughput and latency. Many of the NoC's has buffered and bufferless routers to optimize the area, power consumption and latency. Therefore the detailed literature survey has been done mainly on latest buffered and bufferless NoC's with different routing algorithms used for addressing the major constraints like QoS, throughput, latency and hardware utilizations for different injection rates. As per requirements at present situation for better communication within core networks, this paper mainly focused on commonly used architectures and their inter components connectivity's that can deal with methodologies and design challenges for optimization of signal integrity, scalability, throughput and latency in an NoC's. At the last, modified buffered and bufferless NoC architectures are proposed which includes the modified routing algorithm called Dynamically buffered and bufferless reconfigurable NoC (DB 2 R-NoC's) and feasible direction finding (FDF) for switching. Making use of these architectures, any dimensions of NoC's can be designed and can validate for multimedia data and also can test on Field Programmable Gate Array (FPAG) processors.

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Section: Literature Surveymentioning

confidence: 78%

NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

S.B¹

2020

IJATCSE

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“…At high workload, the congested flow stalls the progress of normal traffic because of HoL blocking. VOQ [23], where each VC corresponds to a single output channel connecting to the adjacent node, can eliminate HoL with high power and hardware complexity and is hard to be used in NoCs [24]. Packets enter corresponding VOQ according to the output channel selection from NRC.…”

Section: Hybrid Memory Buffer With Mixed Queue (Hmmq)mentioning

confidence: 99%

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Lai

Cai

Jie

2023

IEICE Electron. Express

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Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

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“…Another solution is output queued routers, they maintain buffer queues at the output port which are free from HoL blocking but increases write bandwidth when multiple flits are waiting for the same output port. Reorder-Buffer [RoB] router targets low latency by avoiding HoL blocking but the design increases the router's overall critical path delay [32]. In [33] we proposed latency improvement and mitigated HoL blocking by using Fill VC allocation for NoC.…”

Section: Related Workmentioning

confidence: 99%

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

2021

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Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

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RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router

Cited by 19 publications

References 19 publications

NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

NOC’S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

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