Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

De, Sourav; Le, Hoang‐Hiep; Qiu, Bo-Han; Baig, Md. Aftab; Sung, Po-Jung; Su, Chun-Jung; Lee, Yao-Jen; Lu, Darsen D.

doi:10.1109/led.2021.3089621

Cited by 25 publications

(19 citation statements)

References 10 publications

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“…The retention characteristics (Figure. [4,6,8]. However, while the tHZO was greater than 3tIGZO, the erase was possible by applying a negative voltage pulse at the gate terminal, which agrees with the results obtained for the MFSM structure.…”

Section: Experiments and Resultssupporting

confidence: 86%

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Gate-Stack Engineered IGZO-based Multi-bit OTP FeTFT with Lifelong Retention for Inference Engine Applications

De¹

2022

Preprint

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<p>This paper reports back-end-of-line (BEoL) compatible indium gallium zinc oxide (IGZO) based multibit one-time programmable (OTP) ferroelectric thin-film transistors (FeTFT) with lifelong retention capability. The maximum temperature of the entire fabrication process was limited to 350oC. The gate-stack engineering by varying the thickness ratio of hafnium zirconium oxide (HZO) and IGZO layer fomented data-retention capability over ten years and OTP property. Further, we have evaluated the performance of IGZO-based OTP FeTFT as synaptic devices for an inference engine. The system-level simulation revealed inference accuracy loss of only 1.5% after ten years without re-training for Modified National Institute of Standards and Technology (MNIST) hand-written digits in a multi-layer perceptron (MLP) neural network with a baseline of 97%. The proposed inference engine also showed superior energy efficiency and cell area of 95.33 TOPS/W (binary) and 8F2, respectively.</p>

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Section: Experiments and Resultssupporting

confidence: 86%

“…based FeFETs [1][2][3], FefinFETs [4][5][6], and FeTFTs [7,8] have paved the way for further scaling and monolithic 3D integration with thin-film transistors (TFTs). However, the TFTs with polycrystalline silicon channels suffer from retention degradation, high thermal budget, and mobility (µ) degradation [9].…”

Section: Introductionmentioning

confidence: 99%

Gate-Stack Engineered IGZO-based Multi-bit OTP FeTFT with Lifelong Retention for Inference Engine Applications

De¹

2022

Preprint

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“…The successful demonstrations of these devices can be further exploited to implement hardware ANNs. For example, a crossbar array using a three-terminal FeFET can form a basic building block for ANN, as shown in figure 12(a) [100][101][102]. Simultaneously, two-terminal devices using 2D ferroelectrics as the active layer can be integrated to realize the 1T1R structure, as shown in figure 12(b) [103].…”

Section: Challenges and Outlookmentioning

confidence: 99%

Ferroelectric memory based on two-dimensional materials for neuromorphic computing

Chen

Pam

et al. 2022

Neuromorph. Comput. Eng.

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Ferroelectric memory devices with fast-switching speed and ultra-low power consumption have been recognized as promising building blocks for brain-like neuromorphic computing. In particular, ferroelectric memories based on 2D materials are attracting increasing research interests in recent years due to their unique properties that are unattainable in conventional materials. Specifically, the atomically thin 2D materials with tunable electronic properties coupled with the high compatibility with existing complementary metal-oxide-semiconductor (CMOS) technology manifests their potential for extending state-of-the-art ferroelectric memory technology into atomic-thin scale. Besides, the discovery of 2D materials with ferroelectricity shows the potential to realize functional devices with novel structures. This review highlights the recent progress in ferroelectric memory devices based on 2D materials for neuromorphic computing. The merits of such devices and the range of 2D ferroelectrics being explored to-date are reviewed and discussed, which include two- and three-terminal ferroelectric synaptic devices based on 2D materials platform. Finally, current developments and remaining challenges in achieving high-performance 2D ferroelectric synapses are discussed.

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“…Further factors like endurance, latency, and negligible impact from random telegraph noise (RTN) enable HfO2-based ferroelectric memories, especially the FeFETs, as a prospective candidate for next-generation IMC applications [14][15][16][17][18]. Recent research on 28nm high-k metal gate (HKMG) FeFETs, and FefinFETs have enabled the use of deeply scaled memory devices for analog computing-in-memory (CIM) applications [19][20][21][22]. However, device-to-device (D2D) variations in deeply scaled FeFETs pose a severe threat to accurately executing analog vector-matrix multiplication operations.…”

Section: Introductionmentioning

confidence: 99%

“…However, device-to-device (D2D) variations in deeply scaled FeFETs pose a severe threat to accurately executing analog vector-matrix multiplication operations. Numerous efforts have been made to improve the ill-impact D2D variations in FeFETs [20,[22][23][24][25] for neuromorphic computing. One approach is to run online training of NNs with FeFETs as synapses due to their noise-tolerant nature [26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications

Müller

et al. 2022

IEEE J. Electron Devices Soc.

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This paper reports 2bits/cell ferroelectric FET (FeFET) devices with 500 ns write pulse of maximum amplitude 4.5V for inference-engine applications. FeFET devices were fabricated using GlobalFoundries 28nm high-k-metal-gate (HKMG) process flow on a 300mm wafer. The devices were characterized, and statistical modeling of variations in the fabricated devices was carried out based on experimental data. Furthermore, the model was applied to multi-layer perceptron (MLP) neural network (NN) simulations using the CIMulator software platform. The neural network (NN) was trained offline, and the weights were transferred to the synaptic devices for an inference-only operation. Device-to-device (D2D) and cycle-tocycle (C2C) variations are limited by optimal process conditions and do not impact inference accuracy. However, due to short-term retention, read-to-read (R2R) variation significantly affects inference operation. This work proposes a synergistic READoptimization approach to mitigate the impact of short-term retention and device variation issues. The optimization technique fostered immunity in the MLP-NN towards R2R variations, and the MLP-NN maintains inference accuracy of 97.01%, while the software baseline is 98%.

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Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

Cited by 25 publications

References 10 publications

Gate-Stack Engineered IGZO-based Multi-bit OTP FeTFT with Lifelong Retention for Inference Engine Applications

Gate-Stack Engineered IGZO-based Multi-bit OTP FeTFT with Lifelong Retention for Inference Engine Applications

Ferroelectric memory based on two-dimensional materials for neuromorphic computing

READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications

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