Robust detection of soft errors using delayed capture methodology

Prasanth, V.; Singh, Virendra; Parekhji, Rubin

doi:10.1109/iolts.2010.5560188

Cited by 4 publications

(2 citation statements)

References 18 publications

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“…In the delayed capture methodology [24] shown in Figure 1, a single bit parity for a set of flip-flops is calculated and stored in the parity flip-flop. The parity corresponding to the values of the functional flip-flops is calculated and compared with the value in the parity flip flop.…”

Section: Delayed Capture Methodologymentioning

confidence: 99%

“…Circuit level abstraction lies between these two extremes. In these techniques, the structural knowledge of the circuit is utilised to selectively introduce additional hardware for soft error mitigation [11,24]. Here the soft error mitigation technique is applied after considering the error tolerance required and the implementation overhead reduction possible by considering the derating factors.…”

Section: Introductionmentioning

confidence: 99%

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Derating based hardware optimizations in soft error tolerant designs

Prasanth

Singh

Parekhji

2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems.The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

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Section: Delayed Capture Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%