Robustness improvement of an SRAM cell against laser-induced fault injection

Sarafianos, Alexandre; Lisart, Mathieu; Gagliano, Olivier; Serradeil, V.; Roscian, Cyril; Dutertre, Jean-Max; Tria, Assia

doi:10.1109/dft.2013.6653598

Cited by 6 publications

(7 citation statements)

References 12 publications

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“…This has for notable consequence that the robustness improvement relying on this masking effect presented in [18] may not be valid for picosecond range pulses.…”

Section: Discussionmentioning

confidence: 99%

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Lacruche

Borrel

Champeix

et al. 2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

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Abstract-Laser fault injection into SRAM cells is a widely used technique to perform fault attacks. In previous works, Roscian and Sarafianos studied the relations between the layout of the cell, its different laser-sensitive areas and their associated fault model using 50 ns duration laser pulses. In this paper, we report similar experiments carried out using shorter laser pulses (30 ps duration instead of 50 ns). Laser-sensitive areas that did not appear at 50 ns were observed. Additionally, these experiments confirmed the validity of the bit-set/bit-reset fault model over the bit-flip one. We also propose an upgrade of the simulation model they used to take into account laser pulses in the picosecond range. Finally, we performed additional laser fault injection experiments on the RAM memory of a microcontroller to validate the previous results.

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“…This has for notable consequence that the robustness improvement relying on this masking effect presented in [18] may not be valid for picosecond range pulses.…”

Section: Discussionmentioning

confidence: 99%

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Lacruche

Borrel

Champeix

et al. 2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

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“…This approach is ascertained by the very close correlation obtained between simulation and experimental results. This tool proved to be very valuable as it makes it possible to anticipate the laser sensitivity of a circuit before its actual fabrication (as an illustration see the proposal of a laser hardened SRAM design [17]). We also displayed our first results in studying and modeling the laser effects on a FD-SOI 28 nm technology.…”

Section: Discussionmentioning

confidence: 99%

Laser attacks on integrated circuits: From CMOS to FD-SOI

Dutertre¹,

Castro²,

Sarafianos

et al. 2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.

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“…In the following, laser-induced SEEs are described. A laser-induced transient current is then called a 'photocurrent' [8][9][10][11][12][13][14][15][16].…”

Section: A Single Event Effects In Integrated Circuitsmentioning

confidence: 99%

“…Roscian et al [9], Sarafianos et al [8], [12] and Lacruche et al [16] describes the laser sensitivity of SRAM cells. They also develop an effective model for laser pulse durations above 50 ns.…”

Section: Memory Cells Under Pulsed Photoelectrical Laser Stimulationmentioning

confidence: 99%

“…1) Input at '0': When the input is at '0', the OUT node is at '1'. Based on [8], [9], [12], [16], [18], the sensitivity of the cell can be investigated by considering which PN junctions are the most reverse-biased according to the latch state. Indeed, these reverse-biased PN junctions are the place where the electrical field is strong enough to generate a transient current likely to induce an SEU.…”

Section: B Theoretical Photoelectric Sensitive Junctionsmentioning

confidence: 99%

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SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Champeix

Borrel

Dutertre

et al. 2015

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).

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Robustness improvement of an SRAM cell against laser-induced fault injection

Cited by 6 publications

References 12 publications

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

Laser attacks on integrated circuits: From CMOS to FD-SOI

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

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