Route packets, not wires: on-chip interconnection networks

Dally, W.J.; Towles, Brian

doi:10.1109/dac.2001.935594

Cited by 1,067 publications

(1,411 citation statements)

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“…In these cases, the wire capacitance still dominates the energy required for communication, especially in a multihop environment where a 10 mm distance is traversed in smaller steps. However the wire bandwidth, which limits bit-rate on 10 mm wires, has a significantly reduced effect on the achievable bit-rate between adjacent cores, which is a prime motivator for the NoCs paradigm [19]. To this end, a body of works exist proposing approaches to efficient communication over the relatively short interconnects that are expected in these systems.…”

Section: Low-swing Interconnect Circuitsmentioning

confidence: 99%

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Postman

Chiang

2012

ISRN Electronics

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Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.

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Section: Low-swing Interconnect Circuitsmentioning

confidence: 99%

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Postman

Chiang

2012

ISRN Electronics

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“…1 However, the ARM11 MPCoret and PowerPCt E405, which provide multi-CPU designs, occupy 1.8 and 2:0 mm 2 in the same technology, respectively [17,18]. If the link was integrated within a CMP as an interconnection network, the area overhead imposed by the network would be reasonable showing the feasibility.…”

Section: Physical Characteristicsmentioning

confidence: 99%

“…High performance CMP architectures have been gaining the attention of high performance computing community in the past few years. As the demand for network bandwidth increases for CMP, the idea of network-on-chip (NoC) becomes more promising because of performance, power, and scalability requirements for an SoC design [1].…”

Section: Introductionmentioning

confidence: 99%

A variable frequency link for a power-aware network-on-chip (NoC)

Lee

Bagherzadeh

2009

Integration

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“…To reduce power consumption of clock and increase communication performance, extensive research has been conducted into network-on-chip (NoC) systems [1][2][3] . The NoC approach particularly suits communication-dominant on-chip systems.…”

Section: Introductionmentioning

confidence: 99%

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

Guan

Tong

Yang

2010

J. Comput. Sci. Technol.

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For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips, this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper. The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock. Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register, and then control the wrapper to sample input/output data. Sender wrapper and receiver wrapper consist of C elements and threshold gates, which ensure the quasi delay-insensitive characteristics and enhance the robustness. Simulations under different technology corners are implemented based on SMIC 0.18 µm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW. Its advantages of high-throughput, low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.

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Route packets, not wires: on-chip interconnection networks

Cited by 1,067 publications

References 0 publications

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

A variable frequency link for a power-aware network-on-chip (NoC)

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

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