Rule-based optimization of reversible circuits

Abstract

Abstract-Reversible logic has applications in various research areas including lowpower design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.

A shared-cube approach to ESOP-based synthesis of reversible logic

“…All or none of the control lines may be negative controls, and an example of a 3-bit Toffoli gate with a single negative control in its first input is shown in Figure 1(b). The use of negative-control Toffoli gates simplifies a circuit by reducing the number of NOT gates [17,18]. Gate count is a popular cost metric used to evaluate reversible circuits.…”

An Extended Approach for Online Testing of Reversible Circuits

“…A negative control Toffoli (NCT) gate is an MCT gate which has some negative controls [5]. The value on target line is inverted if and only if all positive controls have value 1 and all negative controls have value 0.…”

Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications

“…Most of the approaches above have started from using either a unitary matrix or a truth table as input to their algorithm. In [49], a method called Synthesis with Output Permutation was introduced as a method to take output functions that have been permuted with their original specification in order to provide exact and heuristic approaches to generating Toffoli networks.…”

“…This was meshed in [48] with the transformation based method in [33] to produce an more efficient implementation. In [261], the control-V gates to present a set of transformation rules in order to minimize the synthesized circuit using K-maps. The K-maps are used to extract the circuit to determine which nodes may be deleted to preserve the output calculations and reversibility.…”

“…The resulting waveform is shown in Fig. 5 [3], Measurement [10], Peres [261], RMUX1 [182] and UPG [182] that were simulated or designed using this method. With this schematic layout VHDL code can be automatically generated by Xilinx and require minimal changes to the code to become functional.…”