Runtime verification of embedded real-time systems

Abstract

We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. We design observer algorithms for the time-bounded modalities of ptMTL, which take advantage of the highly parallel nature of hardware designs. The algorithms can be translated into efficient hardware blocks, which are designed for reconfigurability, thus, facilitate applications of the framework in both a prototyping and a post-deployment phase of embedded real-time systems. We provide formal correctness proofs for all presented observer algorithms and analyze their time and space complexity. For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the operator’s time bounds. This result is promising with respect to a self-contained, non-interfering monitoring approach that evaluates real-time specifications in parallel to the system-under-test. We implement our framework on a Field Programmable Gate Array platform and use extensive simulation and logic synthesis runs to assess the benefits of the approach in terms of resource usage and operating frequency.

A survey of challenges for runtime verification from advanced application domains (beyond software)

“…Given the numerous possibilities for implementing RV in hardware, multiple contributions have been made that tackle the ongoing search for improvement of hardwarebased RV monitors. Some solutions address monitoring and verification in a single instance [284]. Here, the verification procedure is mapped into soft-microcontroller units, embedded within the design, and use formal languages such as past-time Linear Temporal Logic (ptLTL).…”

An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems

“…12: ≤ t U r 2 they must be disregarded rather than appended to Γ U r and Γ U f . This concludes that U [2,4] , were met in the interval from time t = 1 to t = 3, when the first pulse of ψ 1 must hold until the rising event on ψ 2 is true at some time step between a and b 2 . The Finite State Machine (FSM) in Figure 3, calculates the result of Until operator with just four states (two bits) 3 .…”

“…Since the correct operation of many CPS applications relies upon the correct timing of the system, both functional and temporal requirements of a CPS must be monitored [4]. This paper focuses on the monitoring of timing constraints in CPS.…”

Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems

“…The same applies to the monitor construction presented in [15]. A solution that allows for a rapidly adjustable evaluation of past-time MTL properties is given in [24]. Compared to ETU-based solutions, however, the used interfaces are not available on commonly available hardware or provide less runtime information, operate at low speeds and are, like JTAG, possibly intrusive.…”