S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis

2016

IEEE Trans. VLSI Syst.

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This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systemson-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock.Index Terms-Adaptive clock, coarse grained reconfigurable architecture (CGRA), dynamic frequency control (DFC), high-level synthesis, runtime reconfiguration. 1063-8210

Section: Resultsmentioning

confidence: 99%

Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control

2016

IEEE Trans. VLSI Syst.

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“…Nine different benchmarks taken from the open source synthesizable SystemC benchmark suite S2CBench [10] were chosen to validate our method shown in Table I. The first benchmark is a 9-tap FIR filter, FFT is a Fast fourier transform.…”

Section: Resultsmentioning

confidence: 99%

Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support

IEEE Embedded Syst. Lett.

2015

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One of the biggest advantages of C-Based VLSI design over traditional RT-level design is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. So far previous works have focuses on either pruning the design space or by creating predictive models in combination with different metaheuristics. In this letter, we present a hierarchical method which makes use of modern HLS tool's options to synthesize functions as functional operators in order to explore these separately. Our method therefore explores each function separately and then performs a merging stage in order to obtain the overall dominating results. Moreover our proposed method detects if any changes in the behavioral description have happened between two exploration executions and only explores those functions which have been affected by the source code changes, while the results of the previous exploration are reused, thus enabling for incremental DSE. Results show that our method is very efficient.Index Terms-Design space exploration (DSE), high-level synthesis, incremental exploration.

“…Table 2 shows the different system configurations ranging from systems with a single master and single slave (S1) to more complex systems with three masters and five slaves (S7). The slaves were taken from the Synthesizable SystemC benchmarks suite (S2CBench) [19], where sobel is a 3×3 edge detection filter, md5c is message digest algorithm for cryptographic applications, fir is a 9-tap FIR filter, interp is a three-stage interpolation filter, bsort is an 8 element sorting algorithm, kasumi is a block cipher, aes is an Advanced Encryption Standard specification, ave8 is an average of 8 number algorithm, and adpcm is an adaptive differential pulse coding decoder encoder.…”

Section: Methodsmentioning

confidence: 99%

Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

Veeranna

2017

J Hardw Syst Secur

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This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojanfree (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the case of BIPs, this is extremely hard, as it is a market still in its infancy. Moreover, it is very difficult to find HW Trojan at the system level as the trigger condition might be visible only when the system is fully functional. Thus, this work proposes the inclusion of a small HW Trojan detection circuit called trust filters to detect HW Trojan at runtime. With the help of cycle-accurate simulation model, it is possible to fine tune these filters so that the overall system has no performance degradation. This can be achieved by exploiting the slack time between the time that a slave returns the data to the master and the time that the master sends new data to the slave. The advantages of using C-based design are multi-fold: (i) It allows the generation of fast cycle-accurate models to measure the exact slack of each BIP mapped as a loosely coupled Hardware Accelerator (HWAcc) slave and (ii) its ability to build the complete SoC using synthesizable Application Programming Interfaces (APIs) and hence allowing the fine tuning of these trust filters. Experimental results show that our proposed architecture is very efficient leading to no performance penalties in many cases and has very small area overhead.Keywords High-level synthesis · Hardware trojan · Behavioral MPSoC · Third party behavioral IP (3PBIP)