High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.Index Terms-Benchmark testing, design automation, high level synthesis.

This paper presents a modified technique of simulated annealing, based on machine learning for effective multi-objective design space exploration in High Level Synthesis (HLS). In this work, we present a more efficient simulated annealing called Fast Simulated Annealer (FSA) which is based on a decision tree machine learning algorithm. Our proposed exploration method makes use of a standard simulated annealer to generate a training set, and uses this set to implement a decision tree. Based on the outcome of the decision tree, the algorithm fixes the synthesis directives (pragmas) which contribute to minimizing/maximizing one of the cost function objectives and continues the annealing procedure using the decision tree. Experimental results show that the average execution time of our proposed tree based simulated annealing algorithm is on average 36% faster than the standard annealer and can be up to 48% faster, while leading to similar results.

No abstract

This work proposes three different methods to automatically characterize heterogeneous MPSoCs com-posed of a variable number of masters (in the form of processors) and hardware accelerators (HWaccs). These hardware accelerators are given as Behavioral IPs (BIPs) mapped as loosely coupled accelerators on a shared bus system ( i.e. AHB, AXI). BIPs have a distinct advantage over traditional RT-level based IPs given VHDL or Verilog: The ability to generate micro-architectures with different area vs. perfor-mance trade-offs from the same description. This is usually done by specifying different synthesis direc-tives in the form of pragmas. This in turn implies that using different mixes of the accelerators' micro-architectures lead to SoCs with unique area vs. performance trade-offs. Two of the three methods proposed are based on cycle-accurate simulations of the complete MPSoC, while the third method accelerates this exploration by performing it on a Configurable SoC FPGA. Exten-sive experimental results compare these three methods and highlight their strengths and weaknesses. * Corresponding author.ten used as HWAccs on these heterogeneous MPSoCs. The International Technology Roadmap for Semiconductors (ITRS) already suggested in 2013 that by 2020 a 10x productivity increase for designing complex SoCs was needed [1] . Two main factors were predicted to help to achieve this goal. The first is the re-use of components. ITRS estimates that around 90% of the SoCs will be composed of re-used components. Secondly, the use of new design methodologies to raise the level of abstraction i.e . HLS. The use of HLS has led to a new market for 3PBIPs. One of the main advantages of BIPs is that they are much easier to re-use than traditional RT-level IPs. Moreover, micro-architectures of different area vs. performance trade-offs can be easily obtained by synthesizing the behavioral description with different synthesis options. This is typically done by setting different synthesis options in the form of pragmas (comments) inserted directly into the source code or through global synthesis options. For example, these options can control how to synthesize arrays (register or RAM), if a function should be inlined or not and if loops should be fully unrolled, partially unrolled, not unrolled or pipelined.FPGA vendors have also embraced this new paradigm and have released their own Programmable or Configurable SoCs (CSoCs), e.g . Altera's Cyclone V SoC and Xilinx's Zynq FPGA. These CSoCs contain multiple embedded cores mainly in the form of ARM Cortex A9 and reconfigurable fabric onto which to map the

No abstract