Safe intrinsic evolution of Virtex devices

Hollingworth, G.; Smith, Steve; Tyrrell, Andy M.

doi:10.1109/eh.2000.869357

Cited by 34 publications

(16 citation statements)

References 5 publications

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“…Obviously, the latter method is more accurate, providing better performance and allows to create self-evolvable hardware systems. On the other hand, the main drawback of the intrinsic approach is the high amount of time lost during the reconfiguration process [15].…”

Section: Ehw At a Glancementioning

confidence: 99%

“…The fact that most of the early practical EHW works were based on the Xilinx XC6200 device family is motivated by the following devices features [15]:…”

Section: A Device-driven Historymentioning

confidence: 99%

“…Researchers started to propose new methodologies and approaches to overcome the limits imposed by the Xilinx Virtex family [4], [15]- [17]. Most of the subsequently proposed FPGA-based approaches can be classified into two categories: Virtual Reconfigurable Circuits (VRCs) and direct bitstream manipulation systems.…”

Section: A Device-driven Historymentioning

confidence: 99%

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A bird's eye view of FPGA-based Evolvable Hardware

Cancare

Bhandari

Bartolini

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Abstract-The Evolvable Hardware research area has achieved very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers. To have a positive impact on the Embedded Design Automation field, Evolvable Hardware systems should start to deal with more complex problems instances efficiently. This paper describes some interesting results achieved so far in the Evolvable Hardware area and gives some hints on what should be done for increasing the efficiency of Evolvable Hardware systems.

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Section: Ehw At a Glancementioning

confidence: 99%

“…The fact that most of the early practical EHW works were based on the Xilinx XC6200 device family is motivated by the following devices features [15]:…”

Section: A Device-driven Historymentioning

confidence: 99%

See 1 more Smart Citation

A bird's eye view of FPGA-based Evolvable Hardware

Cancare

Bhandari

Bartolini

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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show abstract

“…Then the results are downloaded into the hardware. On the contrary, for the intrinsic EH, the evolutionary process is performed wholly or partly in hardware [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

FPGA implementation of a cellular univariate estimation of distribution algorithm and block-based neural network as an evolvable hardware

Jewajinda

Chongstitvatana

2008

2008 IEEE Congress on Evolutionary Computation (IEEE World Congress on Computational Intelligence)

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Abstract-This paper pr esents a har dwar e implementation of evolvable block-based neur al networ k (BBNN) amd a kind of EDAs called cellular compact genetic algor ithm (CCGA) in FPGA. The CCGA and BBNN have cellular -like and ar r ay-like str uctur es which ar e suitable for har dwar e implementation. The implemented har dwar e demonstr ates the completely intr insic online evolution in har dwar e without softwar e r unning on micr opr ocessor s. This wor k contr ibutes to the field of evolvable har dwar e by pr oposing CCGA and a layer -based ar chitectur e to an integr ation of BBNN and CCGA as a kind of evolvable har dwar e.In addition, the pr oposed CCGA efficiently solves the scalable issues by scaling up to the size of BBNN. The pr esented appr oach demonstr ates a new kind of evolvable har dwar e.

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“…The evolution of adders has been well studied in the past [32][33][34][35] and the adder design space is very well understood, particularly in the digital domain. We have suggested that one of the primary uses of development is the learning of a bias that embodies a useful design abstraction.…”

Section: Experiments -Evolving Two Bit Addersmentioning

confidence: 99%

Towards development in evolvable hardware

Gordon

Bentley

Proceedings 2002 NASA/DoD Conference on Evolvable Hardware

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Mapping between genotype and phenotype using a model of biological development has been widely touted as a technique for evolving solutions to large, complex problems [1-3]. Here we describe two test-bed developmental systems for evolvable hardware problems, and compare each to a naive mapping system. We find that designing evolvable developmental systems is not a trivial problem, however early analysis of the evolved structures demonstrates the potential of the generative processes behind development. We also account for the differences between the results of the two systems, highlighting the importance of search space evolvability over size.

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Safe intrinsic evolution of Virtex devices

Cited by 34 publications

References 5 publications

A bird's eye view of FPGA-based Evolvable Hardware

A bird's eye view of FPGA-based Evolvable Hardware

FPGA implementation of a cellular univariate estimation of distribution algorithm and block-based neural network as an evolvable hardware

Towards development in evolvable hardware

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