Symposium on VLSI Technology 1997
DOI: 10.1109/vlsit.1997.623716
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Salicides for 0.10 /spl mu/m gate lengths: a comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co process

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Cited by 13 publications
(6 citation statements)
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“…7 In addition, the high temperatures required to transform C49 TiSi 2 to C54 TiSi 2 on deep-submicron structures, can result in agglomera-tion and degradation of device contact resistance and drive current. 1,2, [9][10][11] An alternative approach, the addition of Mo impurities close to the Ti/Si interface, was shown to result in easier formation of C54 TiSi 2 on submicron structures. 6,8,10,11 In situ x-ray diffraction ͑XRD͒ studies showed that the temperature of the C49 to C54 transformation was reduced for the reaction of Ti with Mo doped single crystal ͑100͒ Si.…”
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confidence: 99%
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“…7 In addition, the high temperatures required to transform C49 TiSi 2 to C54 TiSi 2 on deep-submicron structures, can result in agglomera-tion and degradation of device contact resistance and drive current. 1,2, [9][10][11] An alternative approach, the addition of Mo impurities close to the Ti/Si interface, was shown to result in easier formation of C54 TiSi 2 on submicron structures. 6,8,10,11 In situ x-ray diffraction ͑XRD͒ studies showed that the temperature of the C49 to C54 transformation was reduced for the reaction of Ti with Mo doped single crystal ͑100͒ Si.…”
mentioning
confidence: 99%
“…1,2, [9][10][11] An alternative approach, the addition of Mo impurities close to the Ti/Si interface, was shown to result in easier formation of C54 TiSi 2 on submicron structures. 6,8,10,11 In situ x-ray diffraction ͑XRD͒ studies showed that the temperature of the C49 to C54 transformation was reduced for the reaction of Ti with Mo doped single crystal ͑100͒ Si. 6 Extension of Ti salicide with low sheet resistance to 0.10 m features using Mo impurities 10 and to 0.06 m using Mo impurities and PAI 11 was demonstrated, for low temperature single RTP step processes, with excellent contact resistance and drive currents.…”
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“…Silicides have been used in SALICIDE processes for several CMOS technology nodes [1][2][3][4][5]. For the 45 nm node, modifications or departures from conventional scaling schemes may be necessary, which will impact the integration constraints for silicides, their characteristics or even the way silicides are used in CMOS circuits.…”
Section: Introductionmentioning
confidence: 99%
“…However, using the conventional Ti-salicide process it is difficult to achieve a low resistance in narrow regions due to the incomplete phase transformation from the high-resistivity (phase C49) to the low-resistivity (phase C54) state. In order to enhance the phase transformation without increasing the silicidation temperature, the pre-amorphization implant (PAI) process has been proposed [7][8][9][10][11][12][13][14]. Using the PAI technique, Kittl et al [7] have fabricated and reported on 0.1 µm wide polysilicon Ti-salicide CMOS devices.…”
Section: Introductionmentioning
confidence: 99%