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A novel aluminum plug process is described which offers over a 3x reduction in via resistance as compared with current tungsten plug technology. The performance advantage of the new process is further enhanced by its compatibilty with low thermal budget, low-k dielectric materials, allowing significant reduction in the overall interconnect RC time constant. Key features of the AI plug technology include an over-hang free MOCVD (metal organic CVD) TIN liner, a single step low temperature (260OC) chemical vapor deposition (LTCVD) of aluminum (resistivity < 3 pohm-cm) and copper doping from an overlying PVD AI-Cu film. Double-level metal interconnects with 0.3 pm vias and integrated low-k dielectrics were successfully fabricated using the new CVD TiN/AI technology. The 0.3 pm diameter CVD AI plugs yielded > 3x lower via resistance compared with W plugs (1.5 vs. 5.0 ohms) with no degradation in electromigration reliability. IntroductionAdvanced 0.25 pm interconnects with low-k polymeric dielectrics [I] necessitate the development of low thermal budget (< 4OOOC) processes for plug filling and interconnects. Both tungsten plug and high pressure aluminum extrusion processes [2,3] require process temperatures in excess of 400°C and W plug processes also require an additional etchback step. In this paper, we present an integrated LTCVD/PVD aluminum process for in-situ plug and interconnect formation that is compatible with advanced low-k dielectrics. The low resistivity of aluminum overcomes performance and scaling issues for W plugs in advanced logic and memory devices, and the CVD AI process is adaptable to existing wafer manufacturing equipment and interconnect processes.

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