SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs

He, Miao; Tehranipoor, Mohammad

doi:10.1109/dft.2014.6962097

Cited by 7 publications

(2 citation statements)

References 16 publications

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“…Thus |M| = 1 Kbyte, which is a very low memory cost. The discharge time sensor is accessible by the DTM core (Section II) through cross layer SAMs that reuse DFT and interconnection infrastructure [1], [14], [24].…”

Section: E Area Cost and System Memory Requirementsmentioning

confidence: 99%

“…It collects measurements from on-chip sensors related to the status of the designs (power consumption, temperature, aging, and so on), and optimizes their features (performance, power consumption, temperature, and reliability) by controlling (accordingly) the power-management capabilities of the designs [14]. The interconnection between the designs and the DTM core is achieved through functional interconnection [bus or networkon-chip] [1], shared nonvolatile memory (NVM) [1], and sensor access mechanisms (SAMs) [24]. The DTM core is used for processing data coming from on-chip sensors.…”

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confidence: 99%

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Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

Tenentes

Rossi

Yang

et al. 2017

IEEE Trans. VLSI Syst.

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In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-powernetwork is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

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Section: E Area Cost and System Memory Requirementsmentioning

confidence: 99%

mentioning

confidence: 99%