Sample Preparation Techniques for Reduced Lateral Heat Distribution and Implications for Non-IR Probing on Integrated Circuits

Abstract

Validation techniques on packaged integrated circuit (IC) samples positively impact time to market (TTM) by saving considerable fabrication modification turnaround time and costs. The validation techniques are typically done by working through the backside of the chip. These validation and debug techniques, such as optical probing, use the Solid Immersion Lens (SIL) for imaging and data collection. Solid Immersion Lens based near infrared (NIR) optical probing systems have been an integral function in the product life cycle enabling a fast, reliable, and low defect product to market. For the SIL configuration, the remaining silicon thickness (RST) target is specified to be 50 +/- 5um. The sample preparation tools and techniques to accomplish this have been fully developed and matured enough to provide this specification for all segment form factors. This silicon thickness is also within a sustainable thermal envelope at certain power densities during debug electrical testing and validation. As we move into the next generation of optical probing debug in the visible range, increasing resolution further, new sample preparation methods need to be developed. There are a number of different strategies and techniques to prepare the sample, while also enabling efficient heat transfer. This paper will detail some of the sample preparation techniques as a function of silicon thickness and aspect ratio. These final geometries will then be characterized thermally by investigating lateral heat distribution and junction temperature within the silicon Region of Interest (ROI). Finally, based on this sample preparation and thermal study, implications around debug techniques for optical probing will be discussed.