Microprocessor performance can be significantly improved by lowering the junction temperature, especially down to the deep subambient levels. This provides the strong motivation for the current study, which focuses on the design and thermohydraulic performance evaluation of high heat flux evaporators suitable for interfacing the microprocessor chip with a cascaded R134a∕R508b vapor compression refrigeration system at −80°C. Four compact evaporator designs are examined—a base line slit-flow structure with no microfeatures, straight microchannels, an inline pin fin array, and an alternating pin fin array—all fitting the same size envelope. Pressure drop and heat transfer measurements are reported and discussed to explain the performance of the various evaporator geometries for heat fluxes ranging between 20W∕cm2 and 100W∕cm2.

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Post silicon validation techniques require backside sample preparation by silicon thinning techniques. The conventional fixture to this preparation on large die packages causes silicon to crack. A new “4-point bending” fixture was developed to reduce silicon bending strain during thinning to eliminate silicon cracking. This new fixture and technique improved remaining silicon thickness uniformity as well as process time.

Validation techniques on packaged integrated circuit (IC) samples positively impact time to market (TTM) by saving considerable fabrication modification turnaround time and costs. The validation techniques are typically done by working through the backside of the chip. These validation and debug techniques, such as optical probing, use the Solid Immersion Lens (SIL) for imaging and data collection. Solid Immersion Lens based near infrared (NIR) optical probing systems have been an integral function in the product life cycle enabling a fast, reliable, and low defect product to market. For the SIL configuration, the remaining silicon thickness (RST) target is specified to be 50 +/- 5um. The sample preparation tools and techniques to accomplish this have been fully developed and matured enough to provide this specification for all segment form factors. This silicon thickness is also within a sustainable thermal envelope at certain power densities during debug electrical testing and validation. As we move into the next generation of optical probing debug in the visible range, increasing resolution further, new sample preparation methods need to be developed. There are a number of different strategies and techniques to prepare the sample, while also enabling efficient heat transfer. This paper will detail some of the sample preparation techniques as a function of silicon thickness and aspect ratio. These final geometries will then be characterized thermally by investigating lateral heat distribution and junction temperature within the silicon Region of Interest (ROI). Finally, based on this sample preparation and thermal study, implications around debug techniques for optical probing will be discussed.