SAO in CTU decoding loop for HEVC video decoder

Subramanya, Prashanth Nandalike; Adireddy, Ramakrishna; Anand, Dinesh

doi:10.1109/icspcom.2013.6719845

Cited by 4 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When considering individual filters, a GPU-based DBF has been proposed in [6], where an average performance of 200 FPS and 333 FPS was achieved for All Intra and Low Delay configurations, respectively, in the NVIDIA GeForce 710M GPU. In [17], the authors decreased the frame-level parallelism for the SAO procedure by including it in the CTU decoding procedure, in order to better exploit memory-bandwidth and cache performance. A similar design is proposed in [3] (for CPUs) and in [9], which presents a very low-power programmable coprocessor architecture targeting especially embedded devices.…”

Section: Related Workmentioning

confidence: 99%

GPU Parallelization of HEVC In-Loop Filters

Wang

Souza

Alvarez-Mesa

et al. 2017

Int J Parallel Prog

View full text Add to dashboard Cite

bstract In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC inloop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76 frames per second (FPS) and 125 FPS for Ultra HD 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.

show abstract