SARC Coherence: Scaling Directory Cache Coherence in Performance and Power

Kaxiras, Stefanos; Κεραμίδας, Γεώργιος

doi:10.1109/mm.2010.82

Cited by 56 publications

(48 citation statements)

References 11 publications

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“…This will be driven heavily by the higher power consumption required with increased parallelism and the greater expense in time required to check the increased function unit count for cached copies of data. A number of existing studies provide a description of the challenges and costs associated with this exercise: Schuchhardt et al [14] and Kaxiras and Keramidas [8] provide quantitative evidence that cache coherency creates substantial additional on-chip traffic and suggest forms of hierarchical or dynamic directories to reduce traffic, but these approaches have limited scalability. Furthermore, Xu [20] finds that hierarchical caching doesn't improve the probability of finding a cache line locally as much as one would hope -a conclusion also supported by a completely independent study by Ros et al [12] that found conventional hardware coherence created too much long-distance communication (easily a problem for the scalability of future chips).…”

Section: Cache Locality/topologymentioning

confidence: 99%

Abstract Machine Models and Proxy Architectures for Exascale Computing

Ang

Barrett

Benner

et al. 2014

2014 Hardware-Software Co-Design for High Performance Computing

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To achieve exascale computing, fundamental hardware architectures must change. The most significant consequence of this assertion is the impact on the scientific applications that run on current high performance computing (HPC) systems, many of which codify years of scientific domain knowledge and refinements for contemporary computer systems. In order to adapt to exascale architectures, developers must be able to reason about new hardware and determine what programming models and algorithms will provide the best blend of performance and energy efficiency into the future. While many details of the exascale architectures are undefined, an abstract machine model is designed to allow application developers to focus on the aspects of the machine that are important or relevant to performance and code structure. These models are intended as communication aids between application developers and hardware architects during the co-design process. We use the term proxy architecture to describe a parameterized version of an abstract machine model, with the parameters added to elucidate potential speeds and capacities of key hardware components. These more detailed architectural models are formulated to enable discussion between the developers of analytic models and simulators and computer hardware architects. They allow for application performance analysis and hardware optimization opportunities. In this report our goal is to provide the application development community with a set of models that can help software developers prepare for exascale. In addition, use of proxy architectures, through the use of proxy architectures, we can enable a more concrete exploration of how well application codes map onto the future architectures.

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Section: Cache Locality/topologymentioning

confidence: 99%

Abstract Machine Models and Proxy Architectures for Exascale Computing

Ang

Barrett

Benner

et al. 2014

2014 Hardware-Software Co-Design for High Performance Computing

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show abstract

“…Self-invalidation was recently used by Kaxiras and Keramidas in their "SARC Coherence" proposal [19]. They observe that with self-invalidation, writer prediction becomes straightforward to implement.…”

Section: Self-invalidationmentioning

confidence: 99%

“…In terms of performance and power, complex protocols are characterized by a large number of broadcasts and snoops. Here too, significant effort has been expended to reduce or filter coherence traffic [19,25,34] with the intent of making complex protocols more power-or performance-efficient. Verification of such protocols is difficult and in many cases incomplete [1].…”

Section: Introductionmentioning

confidence: 99%

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Complexity-effective multicore coherence

Ros

Kaxiras

2012

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

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101

102

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Much of the complexity and overhead (directory, state bits, invalidations) of a typical directory coherence implementation stems from the effort to make it "invisible" even to the strongest memory consistency model. In this paper, we show that a much simpler, directory-less/broadcast-less, multicore coherence can outperform a directory protocol but without its complexity and overhead. Motivated by recent efforts to simplify coherence, we propose a hardware approach that does not require any application guidance. The cornerstone of our approach is a dynamic, application-transparent, write-policy (write-back for private data, write-through for shared data), simplifying the protocol to just two stable states. Self-invalidation of the shared data at synchronization points allows us to remove the directory (and invalidations) completely, with just a data-race-free guarantee from software. This leads to our main result: a virtually costless coherence that outperforms a MESI directory protocol (by 4.8%) while at the same time reducing shared cache and network energy consumption (by 14.2%) for 15 parallel benchmarks, on 16 cores.

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“…Relaxed consistency protocols: SC-for-DRF consistency protocols [1], [2], [6], [34], [35] rely on self-invalidation at synchronization points: Lebeck and Wood use self-invalidation to limit the number of cache blocks registered in the directory [6], SARC coherence [34] employs self-invalidation and implements a writer prediction to avoid the directory indirection upon downgrades. In DeNovo [1] a compiler inserts self-invalidating instructions based on source code annotations.…”

Section: Related Workmentioning

confidence: 99%

A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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Abstract-Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers' intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.

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SARC Coherence: Scaling Directory Cache Coherence in Performance and Power

Cited by 56 publications

References 11 publications

Abstract Machine Models and Proxy Architectures for Exascale Computing

Abstract Machine Models and Proxy Architectures for Exascale Computing

Complexity-effective multicore coherence

A Dual-Consistency Cache Coherence Protocol

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