Satisfiability-based test generation for nonseparable RTL controller-datapath circuits

Lingappan, Loganathan; Ravi, S.; Jha, Niraj K.

doi:10.1109/tcad.2005.853700

Cited by 27 publications

(10 citation statements)

References 31 publications

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“…For our experiments, we have used generic RTL/netlists of circuits including Discrete Cosine wave Transform (DCT), Auto-regression Filter (ARF), Application-Specific Programmable Processor (ASSP4) [4], Greatest Common Divisor (GCD), Differential-equation solver (Paulin) [6], Wavelet Transform, and Finite Impulse Response filters (FIR1 and FIR2). In addition to these generic circuits, we have also evaluated the proposed DSP using complex functions such as the Elliptical Wave Filter (EWF), HAL, Smooth Triangle, HornerBezier, Motion Vector, and Matrix Multiplication, starting from their RTL/netlist description.…”

Section: Performance Results and Discussionmentioning

confidence: 99%

Fracturable DSP Block for Multi-context Reconfigurable Architectures

Warrier

Shreejith

Zhang

et al. 2016

Circuits Syst Signal Process

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Multi-context architectures like NATURE enable low-power applications to leverage fast context switching for improved energy efficiency and lower area footprint. The NATURE architecture incorporates 16-bit reconfigurable DSP blocks for accelerating arithmetic computations, however, their fixed precision prevents efficient re-use in mixed-width arithmetic circuits. This paper presents an improved DSP block architecture for NATURE, with native support for temporal folding and run-time fracturability. The proposed DSP block can compute multiple sub-width operations in the same clock cycle and can dynamically switch between sub-width and full-width operations in different cycles. The NanoMap tool for mapping circuits onto NA-TURE is extended to exploit the fracturable multiplier unit incorporated in the DSP block. We demonstrate the efficiency of the proposed dynamically fracturable DSP block by implementing logic-intensive and compute-intensive benchmark applications. Our results illustrate that the fracturable DSP block can achieve a 53.7% reduction in DSP block utilization and a 42.5% reduction in area with a 122.5% reduction in power-delay product without exploiting logic folding. We also observe an average reduction of 6.43% in power-delay product for circuits that utilize NATURE's temporal folding compared to the existing full precision DSP block in NATURE, leading to highly compact, energy efficient designs.

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Section: Performance Results and Discussionmentioning

confidence: 99%

Fracturable DSP Block for Multi-context Reconfigurable Architectures

Warrier

Shreejith

Zhang

et al. 2016

Circuits Syst Signal Process

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show abstract

“…Among the twelve benchmarks we targeted, GCD is Euclid's greatest common divisor 1 implemented in Muttreja et al [2008]. ex1 is the circuit shown in Figure 1, but with a bit-width of 16. ex2 is an RTL circuit from Lingappan et al [2006]. Paulin and diffeq are two differential-equation solvers implemented in Lingappan et al [2006] and Zhong and Jha [2005], and FIR and Biquad are two types of digital filters.…”

Section: Methodsmentioning

confidence: 99%

“…ex1 is the circuit shown in Figure 1, but with a bit-width of 16. ex2 is an RTL circuit from Lingappan et al [2006]. Paulin and diffeq are two differential-equation solvers implemented in Lingappan et al [2006] and Zhong and Jha [2005], and FIR and Biquad are two types of digital filters. ASPP4 is an application-specific programmable processor synthesized in Ghosh et al [1999].…”

Section: Methodsmentioning

confidence: 99%

A hybrid Nano/CMOS dynamically reconfigurable system—Part II

Zhang

Jha

Shang

2009

J. Emerg. Technol. Comput. Syst.

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In Part I of this work, a hybrid nano/CMOS reconfigurable architecture, called NATURE, was described. It is composed of CMOS reconfigurable logic and interconnect fabric, and nonvolatile nano on-chip memory. Through its support for cycle-by-cycle runtime reconfiguration and a highlyefficient computation model, temporal logic folding, NATURE improves logic density and area-delay product by more than an order of magnitude compared to existing CMOS-based field-programmable gate arrays (FPGAs). NATURE can be fabricated using mainstream photo-lithography fabrication techniques. Thus, it offers a currently commercially feasible architecture with high performance, superior logic density, and excellent runtime design flexibility.In Part II of this work, we present an integrated design and optimization flow for NATURE, called NanoMap. Given an input design specified in register-transfer level (RTL) and/or gate-level VHDL, NanoMap optimizes and implements the design on NATURE through logic mapping, temporal clustering, temporal placement, and routing. As opposed to other design tools for traditional FPGAs, NanoMap supports and leverages temporal logic folding by integrating novel mapping techniques. It can automatically explore and identify the best temporal logic folding configuration, targeting area, delay or area-delay product optimization. A force-directed scheduling technique is used to optimize and balance resource usage across different folding cycles. By supporting logic folding, NanoMap can provide significant design flexibility in performing area-delay trade-offs under various user-specified constraints. We present details of the mapping procedure and results for different architectural instances. Experimental results demonstrate that NanoMap can judiciously trade off area and delay targeting different optimization goals, and effectively exploit the advantages of NATURE.

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“…The previous technique is efficient only for circuit models in which: 1) the data and control paths are separate and 2) have design for testability (DFT) [3] support. A SAT-based ATPG technique for non-separable control-datapath circuits is presented in [21]. Techniques that employ word-level reasoning for FTG are reported in the literature.…”

Section: Previous Workmentioning

confidence: 99%

“…Extraction of constraints from a behavioral or register transfer level (RTL) description is a challenging problem [21]. The proposed methodology does solve the problem comprehensively.…”

Section: B Automatic Generation Of the Constraint Model From The Behmentioning

confidence: 99%

Automatic Constraint Based Test Generation for Behavioral HDL Models

Hari

Konda

Kamakoti

et al. 2008

IEEE Trans. VLSI Syst.

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With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.

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Satisfiability-based test generation for nonseparable RTL controller-datapath circuits

Cited by 27 publications

References 31 publications

Fracturable DSP Block for Multi-context Reconfigurable Architectures

Fracturable DSP Block for Multi-context Reconfigurable Architectures

A hybrid Nano/CMOS dynamically reconfigurable system—Part II

Automatic Constraint Based Test Generation for Behavioral HDL Models

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