Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning

Kliem, Daniel; Voigt, Sven-Ole

doi:10.1016/j.micpro.2014.02.006

Cited by 8 publications

(1 citation statement)

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“…Some of them isolate processing cores as much as possible from each other. The architecture proposed in [8], for instance, is based on "local systems" that comprise resources to which the corresponding processing cores have exclusive access. In this approach, physically shared memory is protected by a memory controller that arbitrates transactions from the local systems in a deterministic manner and forwards them to disjoint memory partitions.…”

Section: Related Workmentioning

confidence: 99%

A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems

Dörr

Sandmann

Becker

2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Heterogeneous system-on-chip platforms with multiple processing cores are becoming increasingly common in safetyand security-critical embedded systems. To facilitate a logical isolation of physically connected on-chip components, internal communication links of such platforms are often equipped with dedicated access protection units. When performed manually, however, the configuration of these units can be both time-consuming and error-prone. To resolve this issue, we present a formal model and a corresponding design methodology that allows developers to specify access permissions and information flow requirements for embedded systems in a mostly platform-independent manner. As part of the methodology, the consistency between the permissions and the requirements is automatically verified and an extensible generation framework is used to transform the abstract permission declarations into configuration code for individual access protection units. We present a prototypical implementation of this approach and validate it by generating configuration code for the access protection unit of a commercially available multiprocessor system-on-chip.

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Section: Related Workmentioning

confidence: 99%