Scalability Simulations for Nanomemory Systems Integrated on the Molecular Scale

Abstract

Simulations were performed to assess the prospective performance of a 16 Kbit nanowire-based electronic nanomemory system. Commercial off-the-shelf microcomputer system modeling software was applied to evaluate the operation of an ultra-dense storage array. This array consists of demonstrated experimental non-volatile nanowire diode switches, plus encoder-decoder structures consisting of demonstrated experimental nanowire-based nanotransistors, with nanowire interconnects among all the switching devices. The results of these simulations suggest that a nanomemory of this type can be operated successfully at a density of 10(11) bits/cm(2). Furthermore, modest device alterations and system design alternatives are suggested that might improve the performance and the scalability of the nanomemory array. These simulations represent early steps toward the development of a simulation-based methodology to guide nanoelectronic system design in a manner analogous to the way such methodologies are used to guide microelectronic system design in the silicon industry.

Physically based molecular device model in a transient circuit simulator

“…(14) to polynomial or power-law expansions. While such approaches can be very computationally efficient and may include effects such as negative differential resistance and have been successfully applied in circuit simulators of entire devices [13][14][15][16][17][18][19], their parameters must be fitted to experimental data for each system of interest. Also, approaches such as power-law expansions have unphysical solutions outside of the parameterization range and must always be used with caution.…”

“…Approaches of this type have been quite successful [13][14][15][16][17][18][19] in modelling entire integrated-circuit systems containing nanotubes, DNA wires, and molecular conductors. Features that can be modelled in this way include basic rectification as well as hysteresis loops in which the current is a function of the past voltages as well as the instantaneous voltage, without requiring either excessive memory storage or excessive evaluation times, thus allowing say negative differential resistance to be modelled.…”

Logic synthesis and testing techniques for switching nano-crossbar arrays

“…Previous studies on performance modeling and analysis of nanoarrays lack of accuracy and comprehensiveness. Capacitor-resistor models and their parameter values are determined with weak assumptions without in depth analysis of nanoarray technologies [37]. Additionally, some studies exploit current or predictive technology models for nanoscale CMOS which certainly has major differences from nanoarray based technologies, both in design and manufacturing levels [38,39].…”

Nanoscale Data Storage

“…Nanotubes and nanowires are also being extensively investigated for application in various nanoscale devices [2,13,188]. Besides nanowires/tubes can be used to construct addressable molecular junction arrays [86,89], these nanostructures themselves can be used as information storage media [11,16]. For example, electrical switching has been reported for carbon nanotube Y-junctions [189].…”