Scalable communications for a million-core neural processing architecture

Patterson, Cameron; Garside, Jim; Painkras, Eustace; Temple, Steve; Plana, Luis A.; Navaridas, Javier; Sharp, T. G.; Furber, Steve

doi:10.1016/j.jpdc.2012.01.016

Cited by 9 publications

(11 citation statements)

References 48 publications

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“…This work was motivated by the need to understand how the brain regulates itself to cope with injury. Exploiting the biological adaptive/repair mechanisms of the brain (Stevens, 2008 ) would provide a novel approach to fault tolerant computing, which goes beyond existing capabilities where reliable computations could then be realized using neural networks (Patterson et al, 2012 ), instead of traditional von Neumann computing architectures. Neural networks offer a fine-grained distributed computing architecture that captures to some degree high levels of parallel processing in the brain.…”

Section: Discussionmentioning

confidence: 99%

Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling

Wade¹,

McDaid²,

Harkin³

et al. 2012

Front. Comput. Neurosci.

128

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In this paper we demonstrate that retrograde signaling via astrocytes may underpin self-repair in the brain. Faults manifest themselves in silent or near silent neurons caused by low transmission probability (PR) synapses; the enhancement of the transmission PR of a healthy neighboring synapse by retrograde signaling can enhance the transmission PR of the “faulty” synapse (repair). Our model of self-repair is based on recent research showing that retrograde signaling via astrocytes can increase the PR of neurotransmitter release at damaged or low transmission PR synapses. The model demonstrates that astrocytes are capable of bidirectional communication with neurons which leads to modulation of synaptic activity, and that indirect signaling through retrograde messengers such as endocannabinoids leads to modulation of synaptic transmission PR. Although our model operates at the level of cells, it provides a new research direction on brain-like self-repair which can be extended to networks of astrocytes and neurons. It also provides a biologically inspired basis for developing highly adaptive, distributed computing systems that can, at fine levels of granularity, fault detect, diagnose and self-repair autonomously, without the traditional constraint of a central fault detect/repair unit.

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Section: Discussionmentioning

confidence: 99%

Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling

Wade¹,

McDaid²,

Harkin³

et al. 2012

Front. Comput. Neurosci.

128

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“…Moore et al [18] demonstrate that a large-scale neural simulation is communication-rather than compute-bound, and, in the design of the SpiNNaker CMP, particular emphasis is placed on the communication mechanisms employed [19].…”

Section: B Communicationsmentioning

confidence: 99%

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

Painkras

Plana

Garside

et al. 2013

IEEE J. Solid-State Circuits

Self Cite

416

250

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The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker-Spiking Neural Network architecture-is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.Index Terms-Asynchronous interconnect, chip multiprocessor, energy efficiency, globally asynchronous locally synchronous (GALS), network-on-chip, neuromorphic hardware, real-time simulation, spiking neural networks (SNNs).

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“…GPUs to access memory [3] and maintain process coherency [36], while keeping power consumption lower than on such systems. Each chip can be connected to 6 adjacent neighbours in a toroidal mesh using bi-directional asynchronous links for an aggregate spiking bandwidth of 1.5 Gb/s [37], supporting reconfigurable arbitrary connectivity [16]. Arguably a MC mesh NoC is the most suitable interconnect architecture for reconfigurable neural network implementations [46].…”

Section: Architecturementioning

confidence: 99%

A hierachical configuration system for a massively parallel neural hardware platform

Galluppi

Davies

Rast

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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Simulation of large networks of neurons is a powerful and increasingly prominent methodology for investigate brain functions and structures. Dedicated parallel hardware is a natural candidate for simulating the dynamic activity of many non-linear units communicating asynchronously. It is only scientifically useful, however, if the simulation tools can be configured and run easily and quickly. We present a method to map network models to computational nodes on the SpiNNaker system, a programmable parallel neurallyinspired hardware architecture, by exploiting the hierarchies built in the model. This PArtitioning and Configuration MANager (PACMAN) system supports arbitrary network topologies and arbitrary membrane potential and synapse dynamics, and (most importantly) decouples the model from the device, allowing a variety of languages (PyNN, Nengo, etc.) to drive the simulation hardware. Model representation operates on a Population/Projection level rather than a single-neuron and connection level, exploiting hierarchical properties to lower the complexity of allocating resources and mapping the model onto the system. PACMAN can be thus be used to generate structures coming from different models and front-ends, either with a host-based process, or by parallelising it on the SpiNNaker machine itself to speed up the generation process greatly. We describe the approach with a first implementation of the framework used to configure the current generation of SpiNNaker machines and present results from a set of key benchmarks. The system allows researchers to exploit dedicated simulation hardware which may otherwise be difficult to program. In effect, PAC-MAN provides automated hardware acceleration for

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Scalable communications for a million-core neural processing architecture

Cited by 9 publications

References 48 publications

Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling

Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

A hierachical configuration system for a massively parallel neural hardware platform

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