Scalable High-Performance Phase-Change Memory Employing CVD GeBiTe

Lee, Jinil; Cho, Sunglae; Ahn, Donghwan; Kang, Man-Sug; Nam, Sang-Wan; Kang, Ho–Kyu; Chung, Chee Won

doi:10.1109/led.2011.2157075

Cited by 33 publications

(17 citation statements)

References 14 publications

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“…The emerging memory technologies include various types of memristors. In this section, four types of memristors are discussed: resistive switching, [11][12][13][14][15] phase-change, [16][17][18][19] spintronics, [20][21][22] and ferroelectric. [23][24][25] 2.1.…”

Section: Memristorsmentioning

confidence: 99%

Memristive Devices for New Computing Paradigms

Kim

Jang

2020

Advanced Intelligent Systems

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Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

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Section: Memristorsmentioning

confidence: 99%

Memristive Devices for New Computing Paradigms

Kim

Jang

2020

Advanced Intelligent Systems

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“…Bismuth is one of the dopants in GeTe that has been studied 18 and which has been shown to improve the crystallization speed. 19 Bi has a covalent radius of ∼148 pm, which is significantly larger than that of Ge (∼120 pm) or Te (∼138 pm). Because Bi is known to substitute in Ge sites, 20,21 it creates a size mismatch of >20%, resulting in largescale local atomic disorder.…”

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confidence: 90%

“…The size mismatch would push the ions off-center and create stress fields around the dopants, which can also induce other crystallographic defects in the system. , An ideal dopant would be one which induces maximum possible atomic disorder while not negatively affecting other PCM properties. Bismuth is one of the dopants in GeTe that has been studied and which has been shown to improve the crystallization speed . Bi has a covalent radius of ∼148 pm, which is significantly larger than that of Ge (∼120 pm) or Te (∼138 pm).…”

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confidence: 99%

Low-Power Switching through Disorder and Carrier Localization in Bismuth-Doped Germanium Telluride Phase Change Memory Nanowires

2020

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One of the major problems with phase change memory (PCM) is the high current density required for the crystal–amorphous transformation via a melt-quench process. However, alternative low-energy pathways of amorphization via a defect-assisted process have also been proposed. Here, a defect-assisted amorphization pathway in Bi-doped GeTe nanowires is utilized to establish that carrier localization effects can significantly decrease the energy costs of amorphization. We demonstrate a strategy of doping GeTe nanowires with bismuth to engineer carrier localization effects via Fermi level/mobility edge tuning and increased atomic disorder. Enhanced carrier localization increases the carrier–lattice coupling, and therefore, the energy supplied to carriers via electrical pulses can be more efficiently extracted by the lattice to induce the critical bond distortions required for amorphization without an intermediate melting process. RESET (crystal to amorphous transition) current densities as low as ∼0.3 MA cm–2 are achieved for 8% Bi-doped GeTe nanowires, which is nearly a 3-fold reduction compared to undoped GeTe nanowires and is significantly less than GeTe thin film devices (∼50 MA cm–2). We demonstrate good reversibility of switching in the Bi-doped GeTe nanowires and also demonstrate the existence of intermediate resistance states which can be accessed by controlled electrical pulsing. The combination of low-power switching in conjunction with multiple resistance states indicates that doping strategies in PCM nanowires are beneficial for non-volatile memory and neuromorphic computing applications.

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“…While phase transition processes are well understood and some PCM chips have been manufactured successfully [21][22][23][24][25], SET speed has always been an issue for the realization of future fast speed PCM to meet DRAM like applications. Many efforts have been made to realize high speed of PCM such as the confined-cell, the new chemical vapor deposition technology and new operation method [26][27][28][29][30]. These studies mainly focus on single cell and microstructure characteristic, methods for improving chip level operation speed have not been well studied for embedded application.…”

Section: Introductionmentioning

confidence: 99%

Faster SET Operation in Phase Change Memory with Initialization

Wang

Yuan

Zhang

et al. 2021

IEICE Trans. Electron.

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In conclusion, an initialization method has been introduced and studied to improve the SET speed in PCM. Before experiment verification, a two-dimensional finite analysis is used, and the results illustrate the proposed method is feasible to improve SET speed. Next, the R-I performances of the discrete PCM device and the resistance distributions of a 64 M bits PCM test chip with and without the initialization have been studied and analyzed, which confirms that the writing speed has been greatly improved. At the same time, the resistance distribution for the repeated initialization operations suggest that a large number of PCM cells have been successfully changed to be in an intermediate state, which is thought that only a shorter current pulse can make the cells SET successfully in this case. Compared the transmission electron microscope (TEM) images before and after initialization, it is found that there are some small grains appeared after initialization, which indicates that the nucleation process of GST has been carried out, and only needs to provide energy for grain growth later.

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Scalable High-Performance Phase-Change Memory Employing CVD GeBiTe

Cited by 33 publications

References 14 publications

Memristive Devices for New Computing Paradigms

Memristive Devices for New Computing Paradigms

Low-Power Switching through Disorder and Carrier Localization in Bismuth-Doped Germanium Telluride Phase Change Memory Nanowires

Faster SET Operation in Phase Change Memory with Initialization

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