Scalable min-register retiming under timing and initializability constraints

Abstract

We demonstrate that a maximum-flow-based approach to register-minimization is a useful platform for incorporating varied design constraints. In this work, we extend the flowbased formulation to include timing constraints and to guarantee the existence of an equivalent initial state. Reducing the register count is motivated by positive consequences for physical design, verification, and power consumption, but it is critically necessary for synthesis that these timing and functionality requirements are also met. Our solution is optimum in the number of registers under either or both constraints and also possesses several other distinct advantages: the runtime is significantly faster than comparable techniques, the algorithm is capable of early termination with a timing-feasible solution, and both maximum and minimum path constraints can be specified.

End-to-End Industrial Study of Retiming

“…The min-delay retiming is implemented by combining the relaxation algorithm [1], and the heuristic min-delay algorithm implemented in ABC [17]. The min-area retiming is implemented using constrained min-area retiming algorithm based on max-flow min-cut proposed in [3]. Table II lists the selected experiences results.…”

“…The most recent constrained min-area retiming method was proposed by A. Hurst et. al [3], which the minarea appoach is based on the work of [2]. That approach is developed based on the observation that area-critical and timing-critical regions are rare overlapped.…”

“…The constrained min-area retiming methodology hasn't been changed in the last twenty years, which was proposed by Shenoy et al [16], using a combination of multiple mindelay and min-area retiming. This method works for many designs based on the observation that the regions of area-critical and timingcritical rarely overlap [3]. However, although the optimum solutions can be found, the retiming operations could be very different.…”

“…Despite the progress of the sequential verification, directly check the sequential equivalence is still extremely hard. For example, using model checking technique IC3 [19], it can't directly verify the properties of retimed s13207, s15850, and s38584 ISCAS-89 designs, with more than 24 hours 3 . Engineering Change Order (ECO) is another side challenge of retiming.…”

“…• constrained min-area: minimize the number of registers with a given worst-path delay constrain [3]. Numerous techniques have been proposed in our community to achieve these three objectives [1] [7], and have been demonstrated with encouraging results.…”