Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client

Eeckhaut, Hendrik; Devos, Harald; Lambert, Peter; Schrijver, Davy De; Lancker, Wim Van; Nollet, V.; Avasare, Prabhat; Clerckx, Tom; Verdicchio, Fabio; Christiaens, Mark; Schelkens, Peter; Walle, Rik Van de; Stroobandt, Dirk

doi:10.1109/tmm.2007.906606

Cited by 13 publications

(9 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, other blocks are connected to the switch fabric to build the RE-SUME scalable wavelet-based video decoder described in [13]. It can decode 26.15 frames/s (clocking the DDR at 65 MHz, limited by the FPGA synthesis process).…”

Section: Further Integrationmentioning

confidence: 99%

Constructing Application-Specific Memory Hierarchies on FPGAs

Devos

Campenhout

Verbauwhede

et al. 2011

Transactions on High-Performance Embedded Architectures and Compilers III

View full text Add to dashboard Cite

Abstract. The high performance potential of an FPGA is not fully exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip buffer memories and minimize the number of accesses to off-chip memory. Buffer memories not only hide the external memory latency, but can also be used to remap data and augment the on-chip bandwidth through parallel access of multiple buffers. This paper discusses the differences and similarities of memory hierarchies on processor-and on FPGA-based systems and presents a step-by-step methodology to construct a memory hierarchy on an FPGA.

show abstract

Section: Further Integrationmentioning

confidence: 99%

Constructing Application-Specific Memory Hierarchies on FPGAs

Devos

Campenhout

Verbauwhede

et al. 2011

Transactions on High-Performance Embedded Architectures and Compilers III

View full text Add to dashboard Cite

show abstract

“…For an overview about wavelet based video codecs and a performance analysis as well as techniques used in those codecs see the overview paper by Adami et al [1]. Under similar considerations Eeckhaut et al [5] developed a complete server to client video delivery chain for scalable wavelet-based video. The main concern of research regarding UMA is usually performance with respect to scaling and in-network adaption.…”

Section: Introductionmentioning

confidence: 99%

Selective encryption of the MC EZBC bitstream for DRM scenarios

Hofbauer

Uhl

2009

Proceedings of the 11th ACM Workshop on Multimedia and Security

View full text Add to dashboard Cite

Universal Multimedia Access (UMA) calls for solutions where content is created once and subsequently adapted to given requirements. With regard to UMA and scalability, which is required often due to a wide variety of end clients, the best suited codecs are wavelet based (like the MC-EZBC) due to their inherent high number of scaling options. However, we do not only want to adapt the content to given requirements but we want to do so in a secure way. Through DRM we can ensure that the actual content is safe and copyright is observed. However, traditional encryption removes the option of scalability in the encrypted domain which is opposed to what we want to achieve for UMA. The solution is selective encryption where only a part of the content is encrypted, enough to ensure safety but at the same time little enough to keep scalability intact. Towards this goal we discuss various methods of applying encryption to the bitstream produced by the MC-EZBC in order to keep scalability intact in the encrypted domain while also keeping security intact with regard to various DRM scenarios.

show abstract

“…Significant speedups have been obtained for several application domains: multimedia [Vassiliadis et al 2004;Eeckhaut et al 2007;Lysecky et al 2006], bio-informatics [Maddimsetty et al 2006;Faes et al 2006], and many other applications where small computational kernels with a sufficient amount of internal parallelism are used.…”

Section: Introductionmentioning

confidence: 99%

“…In this article, we concentrate on the latter approach because it uses the hardware only for those specific functions where a significant speedup can be obtained, as has been shown in several hardware implementations [Hakkennes and Vassiliadis 2001;Eeckhaut et al 2007]. Less hardware-friendly methods are left in software.…”

Section: Introductionmentioning

confidence: 99%

Efficient memory management for hardware accelerated Java Virtual Machines

Bertels

Heirman

D’Hollander

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

Application-specific hardware accelerators can significantly improve a system's performance. In a Java-based system, we then have to consider a hybrid architecture that consists of a Java Virtual Machine running on a general-purpose processor connected to the hardware accelerator. In such a hybrid architecture, data communication between the accelerator and the general-purpose processor can incur a significant cost, which may even annihilate the original performance improvement of adding the accelerator. A careful layout of the data in the memory structure is therefore of major importance to maintain the acceleration performance benefits.This article addresses the reduction of the communication cost in a distributed shared memory consisting of the main memory of the processor and the accelerator's local memory, which are unified in the Java heap. Since memory access times are highly nonuniform, a suitable allocation of objects in either main memory or the accelerator's local memory can significantly reduce the communication cost. We propose several techniques for finding the optimal location for each Java object's data, either statically through profiling or dynamically at runtime. We show how we can reduce communication cost by up to 86% for the SPECjvm and DaCapo benchmarks. We also show that the best strategy is application dependent and also depends on the relative cost of remote versus local accesses. For a relative cost higher than 10, a self-learning dynamic approach often results in the best performance.

show abstract

Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client

Cited by 13 publications

References 27 publications

Constructing Application-Specific Memory Hierarchies on FPGAs

Constructing Application-Specific Memory Hierarchies on FPGAs

Selective encryption of the MC EZBC bitstream for DRM scenarios

Efficient memory management for hardware accelerated Java Virtual Machines

Contact Info

Product

Resources

About