Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Thoti, Narasimhulu; Li, Yiming; Kola, Sekhar Reddy

doi:10.1109/vlsi-tsa48913.2020.9203648

Cited by 4 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, an increase in L sov reduces the source-drain distance and origins for strong short channel effects by causing source-drain tunneling. 24 In addition, reasonable drain-overlap (L dov ) is used to compensate for the poor I off of the device. Figure 6, showing the scaled L sov from 2.5 to 10 nm (with step of 2.5 nm).…”

Section: Resultsmentioning

confidence: 99%

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Thoti

2021

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

Ferroelectric materials are promising resources for boosting the performance of line or vertical tunneling-field transistors (VTFETs) by diminishing the voltage requirements. Here, we propose a promising VTFET design which has the benefits of HZO thin films having 50% of Zr composition on Hafnium oxide as Hf 0.5 Zr 0.5 O 2 . The significance of negative capacitance (NC) from Hf 0.5 Zr 0.5 O 2 on to VTFET is explored with the physical factors of the electric field and band-to-band tunneling. In addition, the significant factor of the internal-voltage due to NC is modeled using the metal-ferroelectric-insulator approach. The device on-and off-state currents are optimized with the key factor of vertical tunneling called overlapped source and drain regions for NCVTFET. Using an enhanced vertical tunneling area, hetero-structure (Si/SiGe), and ferroelectric options provides two-time improvement in I on by utilizing the ferroelectric rather than the nominal (without ferroelectric). The device also delivers 40-145 GHz of frequency with low orders (<1.0 fF) of gate-capacitance. The device provides ten-time improvement in I on and two-order reduction in energyefficiency compared to the explored ferroelectric structure.

show abstract

Section: Resultsmentioning

confidence: 99%

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Thoti

2021

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

“…1(c)] is a crucial factor to optimize the performance of line TFETs. 19) Hence the optimized p-epitaxial doping is analyzed based on the controlled I off (to deliver high I on /I off ratio), estimated as 4 × 10 −16 A μm −1 [Fig. 4(a)].…”

Section: Resultsmentioning

confidence: 99%

“…These factors will strongly influence double-gate and planar structures as the channel length reaches the critical value (twice the thickness of the device). 18,19) Therefore, GAA can provide enough controllability by which it can suppress the gate-leakage and DIBT far better than the other geometrical options. Therefore, in this work, by utilizing ferroelectric, scaled line tunneling, and the GAA nanosheet geometry, we design and explore ferroelectric nanosheet line TFETs (FNLTFETs).…”

Section: Introductionmentioning

confidence: 99%

p-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

Thoti¹,

Li²

2021

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

This work illustrates the ample exploitation of ferroelectric through metal-ferroelectric options for nanosheet line tunnel field-effect transistor (NLTFET), for the first time. Here, SiGe and ferroelectric (HZO) are successfully employed to demonstrate the high performance p-NLTFET through simulations. Owing to this, the on-state current (I on = 122.3 μA μm−1) is enormously improved through the reduction of gate-oxide thickness even at low gate bias. In addition, the steep subthreshold swing is effectively minimized to 25.96 mV dec−1 by controlling the off-state current, gate-leakage and trap-assisted-tunneling. Overall, a 2-order boost on the I on is achieved, compared with planar ferroelectric TFETs.

show abstract

Device-Simulation-Based Machine Learning Technique for the Characteristic of Line Tunnel Field-Effect Transistors

Akbar

Thoti

2022

IEEE Access

View full text Add to dashboard Cite

Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Cited by 4 publications

References 4 publications

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

p-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

Device-Simulation-Based Machine Learning Technique for the Characteristic of Line Tunnel Field-Effect Transistors

Contact Info

Product

Resources

About