Scaling Soft Processor Systems

Abstract

As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this paper we explore the organization of processors and caches connected to a single off-chip memory channel, for workloads composed of many independent threads. In particular we design and evaluate real FPGA-based processor, multithreaded processor, and multiprocessor systems on EEMBC benchmarks-investigating different approaches to scaling caches, processors, and thread contexts to maximize throughput while minimizing area. Our main finding is that while a single multithreaded processor offers improved performance over a single-threaded processor, multiprocessors composed of single-threaded processors scale better than those composed of multithreaded processors.

Automatic multithreaded pipeline synthesis from transactional datapath specifications

“…Our synthesis system supports the recently proposed approach to deal with long-latency events based on replay [9,10]. The idea is to allow a pipeline stage to request a replay when it suffers from a long-latency event.…”

“…A known shortcoming of replay [10] is that it may lead to a livelock when the service for a long-latency event for a thread that requested a replay keeps being cancelled by the service of another long-latency event for another thread that also requested a replay (e.g., conflicting cache misses where two cache line requests evict one another). To prevent this, we support a mechanism to turn off replay capability dynamically to guarantee forward progress.…”

“…Other recent works [1,3,9,10,12] also presented design case studies of multithreaded processor pipelines for FPGA prototyping. However these pipelines are manually developed.…”

“…While there are existing works on automatic synthesis of in-order pipelines [4-8, 11, 13, 14, 16], to the best of our knowledge there has not been any for synthesis of in-order multithreaded pipelines. Prior works [1,3,9,10,12] have also presented multithreaded processor pipelines for FPGA prototyping, but they are manually developed.…”

The case for hardware transactional memory in software packet processing

“…Each processor has a single-issue, in-order, 5-stage pipeline that issues instructions from four hardware threads in roundrobin to hide pipeline hazards and cache miss latency [39].…”