Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

Abstract

This article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scan-cell reordering techniques can utilize both high response correlations and pattern correlations to simultaneously minimize scan-out and scan-in transitions. Those scan-shift transitions can be further reduced by selectively using the inverse connections between scan cells. In addition, the trade-off between routing overhead and power consumption can also be controlled by the proposed scan-cell reordering techniques. A series of experiments are conducted to demonstrate the effectiveness of each of the proposed techniques individually.

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

“…Therefore, the shift-out transitions must be considered. The proposed method also outperformed the methods in [ 26 ] and [ 27 ], which considers both the shift-in and -out transitions. The experimental results demonstrated that when applying the proposed method, the power consumption was decreased by 28.31% on average in all the experimental benchmark circuits compared with the previous method.…”

“…Synopsys Design Compiler was used to synthesize the benchmark circuits, Synopsys DFT Compiler was used for the DFT insertion, and Synopsys TetraMax was used to generate patterns and apply X-filling technology. The proposed method was compared with the pattern-based scan chain reordering method [ 26 , 27 ] and the logic topology-based scan chain stitching method [ 28 ] for shift-power reduction. The experiments were conducted using the SAED 32 nm library supported by the Synopsys ARMENIA Education Department.…”

“…In the experiments, the WTMs were measured to confirm the superiority of the proposed method for shift-power reduction compared with the previous method. The performance of the proposed method was compared with state-of-the-art methods [ 26 , 27 , 28 ] using four ISCAS’89 circuits, as shown in Table 2 . The proposed method outperformed that in [ 28 ], which is one of the latest scan reordering methods, by an average of 43.46%.…”

“…Moreover, the same test patterns can be used to test the circuits. Therefore, the test coverage of the proposed method is equivalent to that of [ 26 , 27 , 28 ] and the conventional stitching method. The test times also remain the same during scan testing.…”

“…The method in [ 26 ] used both response and pattern correlations to minimize the scan-out and -in transitions simultaneously. Seo et al proposed a scan chain reordering-aware X-filling and stitching method for the scan-shift power reduction [ 27 ].…”