Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

Seo, Sungyoul; Lee, Yong; Lim, Hyeonchan; Lee, Joo-Hwan; Yoo, Hongbom; Kim, Yojoung; Kang, Sungho

doi:10.1109/ats.2015.8

Cited by 22 publications

(12 citation statements)

References 18 publications

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“…Synopsys Design Compiler was used to synthesize the benchmark circuits, Synopsys DFT Compiler was used for the DFT insertion, and Synopsys TetraMax was used to generate patterns and apply X-filling technology. The proposed method was compared with the pattern-based scan chain reordering method [ 26 , 27 ] and the logic topology-based scan chain stitching method [ 28 ] for shift-power reduction. The experiments were conducted using the SAED 32 nm library supported by the Synopsys ARMENIA Education Department.…”

Section: Resultsmentioning

confidence: 99%

“…The method in [ 26 ] used both response and pattern correlations to minimize the scan-out and -in transitions simultaneously. Seo et al proposed a scan chain reordering-aware X-filling and stitching method for the scan-shift power reduction [ 27 ]. Pathak et al proposed a logic cluster controllability (LoCCo)-based scan chain stitching method that reduces the shift-in power [ 28 ].…”

Section: Related Workmentioning

confidence: 99%

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Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Lee

Cho

Kim

et al. 2021

Sensors

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Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Lee

Cho

Kim

et al. 2021

Sensors

Self Cite

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“…In [3] the test patterns are extracted from the ATPG considering a post-ATPG X-filling. SR-aware X-filling is carried out on ATPG extracted test patterns performed based on pre-computed transition probability (TP).…”

Section: Shift Power Reduction Through Don't Care Bit Fillingmentioning

confidence: 99%

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Mitra¹,

Das²

2018

IJEECS

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Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don’t care bit(X) filling approaches are one of them in this fraternity. These don’t care(X) bit filling techniques have drawn the significant attention of industry and academia for its higher compatibility with existing design flow as neither modification of the CUT is required nor they need to rerun the time-consuming ATPG process. This paper presents an empirical survey of those X-bit filling techniques, applied to mitigate prime two types of dynamic power dissipation namely shift power and capture power, occurred during full scan testing.

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“…Therefore, the key to reducing scan-in power is to decrease the logic state transitions. Typical low-power methods are about scan chain or test pattern reordering [5,6].…”

mentioning

confidence: 99%

“…Except for the row vector v c in the matrix S 1 , a vector that is the most similar to the vector v c will be found from the remaining vectors. This requires calculating the minimum Hamming distance between the remaining vectors and the vector v c according to (6), which is…”

mentioning

confidence: 99%

Double Hamming distance‐based 2D reordering method for scan‐in power reduction and test pattern compression

2020

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A double Hamming distance-based 2D reordering method is proposed for a test set with don't care bits (Xs) to reduce scan-in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering-based methods, the authors' method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more Xs are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '1-0' and '0-1' logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan-in power consumption but also facilitates code-based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state-of-the-art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run-length coding is improved to 73.76% in average utilising their proposed method.

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Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

Cited by 22 publications

References 18 publications

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Double Hamming distance‐based 2D reordering method for scan‐in power reduction and test pattern compression

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