Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

Huang, Yu; Cheng, Wu-Tung; Guo, Ruifeng; Tai, Ting-Pu; Kuo, F. S.; Chen, Yuan-Shih

doi:10.1109/ats.2009.36

Cited by 32 publications

(10 citation statements)

References 11 publications

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“…Some failed on the scan chains and others on logic only. Each logic-only-failure file had up to 256 failing cycles and more failing cycles ECS Transactions, 44 (1) 1029-1035 (2012) were collected for chain failures (10,11). The test time overhead due to datalog collection was negligible because of the efficient test and data logging preparation.…”

Section: Yield Analysis Industrial Casementioning

confidence: 99%

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

Wu¹,

Tai

Chandilya³

et al. 2012

ECS Trans.

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The time to market of a digital device includes first silicon debug, yield ramp and mature yield improvement. Manufacturing test failures caused by defects during mature yield state are usually hard to characterize for advanced technologies and resemble baseline pattern. Diagnosis driven yield analysis (DDYA) is a solution which can be used efficiently during different stages of product life. Instead of relying on just a handful of high quality diagnosis results, it takes volume layout-aware diagnosis results, performs yield analysis, identifies systematic signature, facilitates root cause analysis, and picks the best candidate die for physical failure analysis (FA). The confirmed PFA result can then be used to adjust fabrication process to improve baseline yield and reduce future occurrences of such failures. Case study in this paper shows this flow helped improve a mature yield by 1.7%.

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Section: Yield Analysis Industrial Casementioning

confidence: 99%

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

Wu¹,

Tai

Chandilya³

et al. 2012

ECS Trans.

Self Cite

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“…This is because the faulty values during scan chain loading procedures could be propagated to faulty chain itself and will compromise signal profiling results; and 2) it cannot be applied to circuit with embedded compression logic without using bypass mode. In [28] and [29], an adaptive signal profiling algorithm using manufacturing ATPG patterns have been proposed.…”

Section: Previous Workmentioning

confidence: 99%

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

Kundu¹,

Chattopadhyay

Sengupta

et al. 2015

IEEE Trans. VLSI Syst.

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Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.

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“…3 shows the conventional diagnosis procedure for scan chain faults. In Step 1, faulty chains and fault types (stuck-at-0/stuck-at-1/slow-to-rise/slow-to-fall/slow/fast-torise/fast-to-fall/fast) are determined by using chain test patterns (TPs) consisting of shift-ins and shift-outs without pulsing the capture-clocks [3,6]. In Step 2, both the upper and lower bounds of the faulty scan cells are determined by simulating the failing system logic TPs.…”

Section: Scan-based Diagnosismentioning

confidence: 99%

“…It is important to quickly localize faults on the scan chains for FA in yield enhancement. Therefore, diagnosis for scan chain faults has been widely studied [3][4][5][6][7]. Scan chain fault diagnosis basically consists of three steps: 1) identify the faulty chains and fault types, 2) determine the upper and lower bounds of faulty scan cells, and 3) score and rank the candidates using fault simulation.…”

Section: Introductionmentioning

confidence: 99%

Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors

Nikaido

Funatsu

Seiyama

et al. 2013

2013 22nd Asian Test Symposium

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This work presents our improvement of the failure localization techniques of logic circuits using voltage contrast (VC) in yield enhancement. VC analysis is known as a useful technique for finding defects by comparing scanning electron microscope (SEM) images of a faulty device with those of a good device. However, the observation region in VC analysis should be narrowed down in advance and then failure analysis (FA) engineers need to find small differences in the SEM images in order to make it effective. We improved the software tools of the scan-based diagnosis and VC analysis support to overcome these difficulties. A hybrid technique using the fail data in both the bypass and compression modes in chain fault diagnosis reduces the diagnosis time while suppressing the amount of data explosion concerning the faulty chains. In VC analysis, accurate VC images were emulated from the design layout by taking into account the states of the transistors in the FA phase such as the "on/off" states, gate leakage, and short to ground of the power lines. FA engineers can localize the fault sites with an anomalous contrast by cross-matching between a SEM image of a faulty device and the emulated VC image without using a SEM image of a good device. These techniques accelerate the failure localization in yield enhancement and we demonstrate some examples in this paper.

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Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

Cited by 32 publications

References 11 publications

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors

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