Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Lim, Hyun-Kyu; Cheong, Minho; Kang, Sungho

doi:10.3390/s20174771

Cited by 6 publications

(5 citation statements)

References 36 publications

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“…The full scan method results high test coverage and fault coverage, but as explained earlier this method leaves a problem, namely hardware size and gate overhead which leads to manufacturing costs as the chip gets bigger. In overcoming this problem, in recent years with the increasing need for chips, especially those used in the IoT field, optimization of the layout design chip is needed in order to reduce the cost of the increasingly large chip as done by [14].…”

Section: Resultsmentioning

confidence: 99%

“…The idea of a scanchain is basically adding additional inputs to the flip flop, standard input and scan input data as in Figure 5. The control signal or scan_enable is used to select the input standard for a scan of the input data as, then a scan-chain is formed by connecting the output of one flip flop to the scan data input of another flip flop [14] as shown in Figure 6. The end of this scan-chain is the final circuit that will be tested as shown in Figure 7.…”

Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

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Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.

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Section: Resultsmentioning

confidence: 99%

Section: Modification Process By Adding a Scan-chainmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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show abstract

“…Using design-for-testability (DFT) [7] can make a bus controller work more reliably and stably. One of the methods of DFT is scanning design [8][9][10][11], which can effectively improve the reliability of testing. Testability optimization can address the current shortcomings in the testability of a system by taking appropriate measures via certain means to meet the testability requirements of the system.…”

Section: Introductionmentioning

confidence: 99%

Sequential-Fault Diagnosis Strategy for High-Speed Train Traction Systems Based on Unreliable Tests

Zhou

Jia

et al. 2023

Applied Sciences

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A train traction system is an important part of an urban rail transit system. However, a train traction system has many components and a high risk of internal faults. How to systematically evaluate the fault coverage and diagnosis ability of testing equipment is a fundamental problem in the technical field of train operation. In response to this problem, this study attempts to apply testability technology to the test capability analysis of train traction systems for rail transit. In view of the uncertainty in actual tests, a method for constructing a fault diagnosis strategy for a traction system under unreliable testing is proposed. The concept of test credibility is introduced for the first time, and the quantitative evaluation of test credibility is realized using a cloud model, so as to construct a new “fault-test” credibility correlation matrix. On this basis, a single-fault diagnosis strategy of the traction system is constructed and compared based on information theory. The results show that a using a fault diagnosis strategy under the condition of unreliable testing is more similar to actual maintenance work, proving the significance of the diagnosis strategy constructed using this method for the practical application of the project.

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“…For the accuracy of the cryptographic algorithm, cryptographic circuits must be rigorously tested to guarantee their quality [ 7 ]. Therefore, a scan architecture known as design for testability (DFT) technique, which can obtain high test coverage, is generally used to test the cryptographic circuits [ 8 ]. However, the cryptography circuits consume a high power because they require high computational power.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Lee

Cho

Kim

et al. 2021

Sensors

Self Cite

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Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

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Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Cited by 6 publications

References 36 publications

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Sequential-Fault Diagnosis Strategy for High-Speed Train Traction Systems Based on Unreliable Tests

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

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