Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption

Zhang, Yucong; Holst, Stefan; Wen, Xiaoqing; Miyase, Kohei; Kajihara, Seiji; Qian, Jun

doi:10.1109/ats.2017.37

Cited by 5 publications

(2 citation statements)

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“…Zhang et al [34] presented a method to create scan chain groups to be shifted one at a time instead of shifting simultaneously to reduce shift power consumption. It focuses on the problem of scan cell data retention due to excessive IR-drop during shifting test patterns.…”

Section: Ordering Chains Based On Logic Connectivitymentioning

confidence: 99%

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Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Ordering Chains Based On Logic Connectivitymentioning

confidence: 99%

“…Scan stitching proposed in [33] Figure 5. Data corruption due to simultaneous shifting of chains [34] Zhang et al [35] extended the technique to mitigate shift timing failures caused by excessive IR-drop on clock buffers. Similar to [34], it uses netlist and layout information.…”

Section: Ordering Chains Based On Logic Connectivitymentioning

confidence: 99%