Scheduling for an Embedded Architecture with a Flexible Datapath

Schilling, Thomas; Själander, Magnus; Larsson-Edefors, Per

doi:10.1109/isvlsi.2009.6

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…These architectures usually contain a large number of PUs with local storage. However, their current compiler technology (Lee et al 1998;Smith et al 2006;Aijö et al 2016;Guo et al 2006;Schilling et al 2009), although utilizing register bypassing, still relies on classic code generators where the use of a minimal number of registers is in the focus rather than maximizing the degree of ILP. In , we therefore suggested a code generation technique for exposed datapath architectures that is based on a breadth-first traversal rather than the classic depth-first traversal (Sethi and Ullman 1970) over the syntax trees.…”

Section: Motivationmentioning

confidence: 99%

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Dahlem

Bhagyanath

Schneider

2018

Theory and Practice of Logic Programming

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Conventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the relatively low number of programmer-visible registers. Therefore, more recent processor architectures expose their datapaths so that the compiler (1) can schedule parallel instructions to different processing units and (2) can make effective use of local storage of the processing units. Among these architectures, the Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture whose processing units are equipped with first-in first-out (FIFO) buffers at their input and output ports.In contrast to register-based machines, the optimal code generation for SCAD is still a matter of research. In particular, SAT and SMT solvers were used to generate optimal resource constrained and optimal time constrained schedules for SCAD, respectively. As Answer Set Programming (ASP) offers better flexibility in handling such scheduling problems, we focus in this paper on using an answer set solver for both resource and time constrained optimal SCAD code generation. As a major benefit of using ASP, we are able to generate all optimal schedules for a given program which allows one to study their properties. Furthermore, the experimental results of this paper demonstrate that the answer set solver can compete with SAT solvers and outperforms SMT solvers. This paper is under consideration for acceptance in TPLP.

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Section: Motivationmentioning

confidence: 99%

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Dahlem

Bhagyanath

Schneider

2018

Theory and Practice of Logic Programming

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“…b) Ordering: When scheduling a basic block, the goal is to create a compact schedule. The scheduling is done by greedily selecting as many instructions as possible according to a priority function, while using each limited resource, such as ALU, memory and multiplier, only once [6]. An instruction can only be scheduled if all the instructions it depends on are already scheduled.…”

Section: ) Flexcomp -The Compilermentioning

confidence: 99%

Design space exploration for an embedded processor with flexible datapath interconnect

Hoang

Jalmbrant

Hagopian

et al. 2010

ASAP 2010 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors

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The design of an embedded processor is dependent on the application domain. Traditionally, design solutions specific to an application domain have been available in three forms: VLIW-based DSP processors, ASICs and FPGAs; each respectively offering generality of application domain, energy efficiency and flexibility. However, while matching the application domain to the resources needed, the design space becomes huge. We present FlexTools, a tool framework built around the FlexCore architecture to evaluate performance and energy efficiency for different applications. Here we demonstrate FlexTools for design space exploration with a focus on the data-routing flexibility of the FlexCore processor, in search of energy-efficient interconnect configurations that are both cycle-count and hardware efficient. Evaluation results suggest that a well-optimized instance of a 65-nm multiplier-extended FlexCore processor datapath, obtained using FlexTools, executes nine integer EEMBC benchmarks with a 15% cycle count reduction and dissipates 17% less energy than a reference MIPS datapath.

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