Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation

Gevinti, Eleonora; Cerati, Lorenzo; Biccari, Leonardo Di; Ballarin, Giuseppe; Andreini, A.; Fragnoli, Mauro; Bogani, Antonio

doi:10.1109/eosesd.2015.7314770

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Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation

Cited by 6 publications

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Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II

Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications

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