Schottky Barrier Silicon Nanowire SONOS Memory With Ultralow Programming and Erasing Voltages

Shih, Chun‐Hsing; Chang, Wei Ting; Luo, Yan-Xiang; Liang, Ji-Ting; Huang, M.C.Y.; Chien, Nguyen Dang; Shia, Ruei-Kai; Tsai, Jr-Jie; Wu, Wen−Fa; Lien, Chenhsin

doi:10.1109/led.2011.2164510

Cited by 17 publications

(13 citation statements)

References 15 publications

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“…The memory window of the reconfigurable nonvolatile transistor is 0.25 and 0.35 V for p‐type and n‐type nonvolatile operation, respectively, at I d = 50 pA ( I d · L / W = 3.75 nA; L = 1.5 µm; W = 20 nm). The observed memory window is lower compared to the conventional nonvolatile SONOS flash memories or other nonvolatile Schottky barrier transistors using nanomaterials . The results obtained in our reconfigurable transistor can be attributed to the thick SiO 2 tunnel layer and the absence of a block oxide between the silicon nitride layer and the gate metal.…”

Section: Resultsmentioning

confidence: 72%

“…The observed memory window is lower compared to the conventional nonvolatile SONOS flash memories or other nonvolatile Schottky barrier transistors using nanomaterials. [23][24][25][26] The results obtained in our reconfigurable transistor can be attributed to the thick SiO 2 tunnel layer and the absence of a block oxide between the silicon nitride layer and the gate metal. Much thinner tunnel oxide together with a top oxide will allow us to fully reconfigure the device in a nonvolatile fashion with smaller program and erase voltages.…”

Section: Wwwadvelectronicmatdementioning

confidence: 78%

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Reconfigurable Si Nanowire Nonvolatile Transistors

Park

Jeon

Piontek

et al. 2017

Adv Elect Materials

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circuits. [2,3] The fine-grain reconfiguration approaches aim at the reduction of routingrelated delays and chip area reduction. A very interesting fine-grain approach that emerged during the last decade is based on polarity programmable or reconfigurable field-effect transistors (RFETs). RFETs have been highlighted due to their novel functionality providing both n-type and p-type field-effect transistor (FET) function in a single device selected simply by an electric signal. [4][5][6][7][8][9] Up to date, reconfigurable transistors have been limited to dynamic programming on the function, i.e., a constant program signal needs to be applied to maintain the required function.However, a nonvolatile component that can be embedded into these reconfigurable logic devices would not only eliminate the requirement of having the configuration voltage applied continuously but would also bring additional advantages in terms of multivalent memory operation and close proximity between memory and logic. A number of demonstrations of nanowire-based nonvolatile memory cells have been reported in literature. [10][11][12] In these realizations, the channel polarity of the memory cell is determined by the doping type of silicon. First demonstrators of nonvolatile reconfigurable device operation were shown with the use of a common back gate electrode; [13] in the work by Schwalke et al., the charge trapping is performed using the buried oxide while a high voltage is applied to the global back gate. With this approach, it is difficult to individually address the desired device and to perform other operations in the chip, while writing/erasing some of the devices. Recently, a poly-Si reconfigurable device with a bottom gate array was also demonstrated and showed nonvolatile functionality. [14] In this work, the first demonstration of individually addressable nonvolatile RFETs based on bottom-up grown Si nanowire is presented. Figure 1 shows a schematic design and a crosssectional transmission electron micrograph (TEM) image of the fabricated and measured device. We make use of charge trapping in the gate stack of a dedicated gate electrode. As a vehicle to verify our proof of principle, we integrated the technologically lean charge trapping metal-nitride-oxide-silicon (MNOS) gate stack. The validity of the MNOS stack for nonvolatile charge storage, in general, is well accepted in the memory community. [15,16] For simplicity, in demonstrating the concept, we use a rather thick Si 3 N 4 layer of 15 nm and omit the use of a top blocking oxide. In this configuration, the top part of the thick trapping layer has the same electrostatic function as the blocking oxide in the silicon-oxide-nitride-oxide-silicon Reconfigurable transistors merge unipolar p-and n-type characteristics of field-effect transistors into a single programmable device. Combinational circuits have shown benefits in area and power consumption by fine-grain reconfiguration of complete logic blocks at runtime. To complement this volatile programming technology, a proof of ...

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Section: Resultsmentioning

confidence: 72%

Section: Wwwadvelectronicmatdementioning

confidence: 78%

Reconfigurable Si Nanowire Nonvolatile Transistors

Park

Jeon

Piontek

et al. 2017

Adv Elect Materials

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“…Recently, Schottky barrier source/drain has proposed in multi-bit/cell charge-trapping memory cells for its unique source-side injection programming [1]- [5]. The special Schottky barrier source/drain junctions can produce a strong enhancement of the hot-carrier generation to have a large gate current at low voltages [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

“…The special Schottky barrier source/drain junctions can produce a strong enhancement of the hot-carrier generation to have a large gate current at low voltages [6]- [8]. Enhanced programming and improved characteristics were demonstrated numerically and experimentally [1]- [5]. The effect of dopant-segregated (DS) layers on the source-side injection programming has been discussed to show the differences of physical mechanisms between the DS-structured and the non-DS Schottky barrier cells [1].…”

Section: Introductionmentioning

confidence: 99%

Iterative programming analysis of dopant-segregated multibit/cell Schottky barrier charge-trapping memories

Chen

Tsai

Luo

et al. 2015

2015 15th Non-Volatile Memory Technology Symposium (NVMTS)

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This work numerically elucidates the effects of dopantsegregated layers on the cell window in multi-bit Schottky barrier charge-trapping cells. Successive injection-trapping iteration analysis was performed to properly study the coupling of trapped charges and Schottky barrier lowering during cell programming. The results showed the dopant-segregated profiles have a key function in determining the programming cell window as well as the physical injection mechanism in multi-bit/cell Schottky barrier charge-trapping cells using the forward and reverse reading scheme.

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“…19,20 The nickel silicide source/drain of GAA SiNW SONOS memory are expected to be highly efficient for programming/erasing. 21 However, SiNW device fabrication on bulk oxide substrate, the self-heating effect becomes especially aggravated because low thermal conductivity of buried oxide isolates SiNW from the silicon substrate. 22 Therefore, the thermal effect related to the electrical characteristics of SiNW device are expected to be pronounced in future applications.…”

mentioning

confidence: 99%

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

Chang

Lee

et al. 2012

ECS J. Solid State Sci. Technol.

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A Novel structure and high performance of the Schottky barrier source/drain gate-all-around (GAA) poly-Si nanowire (SiNW) nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is reported with transistor characteristics, efficient programming/erasing, and reliability. The non-uniform thermal stress distribution on SiNW channel due to thermal insulation from the substrate by the buried oxide layer could affect carrier transport behavior. Under a high lateral electric field, the impact ionization is found since a large lateral field enhances carrier velocity. As gate voltage increases, the difference of the drain current between higher and room temperatures can be reduced because a high gate field lowers the Schottky barrier height of source/drain to ensure a strong hot-carriers generation. In particular, the ambipolar conduction of the Schottky barrier source/drain devices promotes the amount of hot-electron injecting programming by positive gate voltage, whereas the Schottky barrier enhances the generation of hot-holes at negative gate voltage to carry out erasure. The proposed Schottky barrier SONOS memory device provides low-voltage and high efficiency programming/erasing without apparent degradation of data retention and 10-K cycling endurance.As the scaling technology down to the 22 nm node and beyond, the planar architectures in very-large-scale integration (VLSI) have shown electrical degradation. 1,2 This stimulates researchers to develop novel structures such as fin-shaped field-effect transistors FETs (FinFET), tunnel FET, nanowire FET, and silicon-on-insulator (SOI) FET as alternative for future 22 nm devices. 3-5 Furthermore, due to conventional ions diffused source/drain (S/D) definition used in MOS-FET structures, the short channel effect becomes severe and obstructs MOSFET and memory cell continued aggressively scaling. Therefore, the nonplanar device structures incorporated better electrostatic control of channel potential that have emerged from the semiconductor industry to be the most attracted candidate to conquer the limitation of continued shrinkage in conventional MOSFETs and improve planar type of nonvolatile memory performance. 6-9 Among them, the adoption of FinFET SONOS memory shows potential for scaling capability and also represents charge-trap silicon-oxide-nitride-oxide-silicon (SONOS) memory with superior gate-control capability and local field enhancement. It can apparently improve the short-channel effect and dramatically enhance programming and erasing efficiency. 10-12 In particular, silicon nitride (SiN) acted as a storage node that resists, few electrons escape because charges are stored at a deep trap level, and, thus, the retention issue is immune to tunnel oxide defects. 13,14 Recently, a novel structure, the gate-all-around (GAA) silicon nanowire (SiNW) MOSFET proposed similar advantages to Fin-FET SONOS. FinFET SONOS has emerged from nano-scale devices due to compatible VLSI process flow and excellent electrical results. 15,16 The benefit of a smaller diamete...

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Schottky Barrier Silicon Nanowire SONOS Memory With Ultralow Programming and Erasing Voltages

Cited by 17 publications

References 15 publications

Reconfigurable Si Nanowire Nonvolatile Transistors

Reconfigurable Si Nanowire Nonvolatile Transistors

Iterative programming analysis of dopant-segregated multibit/cell Schottky barrier charge-trapping memories

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

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