Secure Interposer-Based Heterogeneous Integration

Khan, M. Shafkat M.; Xi, Chengjie; Khan, Aslam A.; Rahman, Mir Tanjidur; Tehranipoor, Mohammad; Asadizanjani, Navid

doi:10.1109/mdat.2022.3151020

Cited by 25 publications

(7 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(2) The Concealment of HTs Increases. Chiplet-based SoW poses new challenges to hardware security, as mentioned in [21][22][23][24][25][26], where third-party chiplet suppliers can implant a single HT's trigger logic and payload logic into separate chiplets. When the trigger logic in one chiplet is activated, it triggers the malicious payload logic located in another chiplet through the communication channel between chiplets, as shown in Figure 3.…”

Section: Motivationmentioning

confidence: 99%

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Mei,

Zhu,

et al. 2024

IET Information Security

View full text Add to dashboard Cite

System on Wafer (SoW) based on chiplets may be implanted with hardware Trojans (HTs) by untrustworthy third-party chiplet vendors. However, traditional HTs protection techniques cannot guarantee complete protection against HTs, which poses a great challenge to the hardware security of SoW. In this paper, we propose a computing architecture based on endogenous security theory—dynamic heterogeneous redundant computing architecture (DHRCA) that can tolerate and detect HTs at runtime. The security of our approach is analyzed by building a generalized stochastic coloring petri net (GSCPN) model of DHRCA. The simulation results based on the GSCPN model show that our method can improve the system security probability to 0.8690 and the system availability probability to 0.9750 in the steady state compared with typical triple-mode redundancy and runtime monitoring methods. Furthermore, the impact of different attack and defense strategies on system security of different methods is simulated and analyzed in this paper.

show abstract

Section: Motivationmentioning

confidence: 99%

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Mei,

Zhu,

et al. 2024

IET Information Security

View full text Add to dashboard Cite

show abstract

“…Multiple IC chips or chiplets are assembled on an interposer for packaging and to be protected from SC attacks or even physically intrusion attacks. A variety of engineering approaches have been proposed in packaging techniques for security [26][27] [28].…”

Section: Attack Protections -Secure Packagingmentioning

confidence: 99%

Design of Circuits and Packaging Systems for Security Chips

Nagata

2023

IEICE Trans. Electron.

View full text Add to dashboard Cite

Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

show abstract

“…Other hardware security studies related to 2.5D/3D integration primarily focus on supply chain vulnerabilities, such as the presence of malicious chiplets (in the form of both software and hardware Trojans) and IP piracy [ 73 , 74 , 75 , 76 ]. For example, an active interposer in a 2.5D system can be leveraged as a root-of-trust to host a hardware security module and various security features, assuming that the interposer is designed and fabricated by trusted entities [ 77 ]. This approach, however, is highly vulnerable to semi-invasive and invasive physical attacks, since the interposer is relatively accessible to a malicious user who can, potentially, bypass these security features while maintaining the functionality of the chiplets.…”

Section: Covert Channel Attacks In 25d/3d Icsmentioning

confidence: 99%

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems

Miketic

Dhananjay

Salman

2023

Sensors

View full text Add to dashboard Cite

In this paper, first, a broad overview of existing covert channel communication-based security attacks is provided. Such covert channels establish a communication link between two entities that are not authorized to share data. The secret data is encoded into different forms of signals, such as delay, temperature, or hard drive location. These signals and information are then decoded by the receiver to retrieve the secret data, thereby mitigating some of the existing security measures. The important steps of covert channel attacks are described, such as data encoding, communication protocol, data decoding, and models to estimate communication bandwidth and bit error rate. Countermeasures against covert channels and existing covert channel detection techniques are also summarized. In the second part of the paper, the implications of such attacks for emerging packaging technologies, such as 2.5D/3D integration are discussed. Several covert channel threat models for 2.5D/3D ICs are also proposed.

show abstract

Secure Interposer-Based Heterogeneous Integration

Cited by 25 publications

References 9 publications

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Design of Circuits and Packaging Systems for Security Chips

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems

Contact Info

Product

Resources

About